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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TIC12400-Q1 scps260 ? august 2017 TIC12400-Q1 24-input multiple switch detection interface (msdi) with integrated adc and adjustable wetting current for automotive systems 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to 125 c ambient operating temperature ? device hbm esd classification level h2 ? device cdm esd classification level c4b ? designed to support 12-v automotive systems with over-voltage and under-voltage warning ? monitors up to 24 direct switch inputs with 10 inputs configurable to monitor switches connected to either ground or battery ? switch input withstands up to 40 v (load dump condition) and down to ? 24 v (reverse polarity condition) ? 6 configurable wetting current settings: (0 ma, 1 ma, 2 ma, 5 ma, 10 ma, and 15 ma) ? integrated 10-bit adc for multi-position analog switch monitoring ? integrated comparator with 4 programmable thresholds for digital switch monitoring ? ultra-low operating current in polling mode: 68 a typical (t poll = 64 ms, t poll_act = 128 s, all 24 inputs active, comparator mode, all switches open) ? interfaces directly to mcu using 3.3 v / 5 v serial peripheral interface (spi) protocol ? interrupt generation to support wake-up operation on all inputs ? integrated battery and temperature sensing ? 8 kv contact discharge esd protection on input pins per iso-10605 with appropriate external components ? 38-pin tssop package 2 applications ? body control module and gateway ? automotive lighting ? heating and cooling ? power seats ? mirrors 3 description the TIC12400-Q1 is an advanced multiple switch detection interface (msdi) designed to detect external switch status in a 12-v automotive system. the TIC12400-Q1 features an integrated 10-bit adc to monitor multi-position analog switches and a comparator to monitor digital switches independently of the mcu. detection thresholds can be programmed for the adc and the comparator to support various switch topologies and system non- idealities. the device monitors 24 direct switch inputs, with 10 inputs configurable to monitor switches connected to either ground or battery. 6 unique wetting current settings can be programmed for each input to support different application scenarios. the device supports wake-up operation on all switch inputs to eliminate the need to keep the mcu active continuously, thus reducing power consumption of the system. the TIC12400-Q1 also offers integrated fault detection, esd protection, and diagnostic functions for improved system robustness. the TIC12400-Q1 supports 2 modes of operations: continuous and polling mode. in continuous mode, wetting current is supplied continuously. in polling mode, wetting current is turned on periodically to sample the input status based on a programmable timer, thus the system power consumption is significantly reduced. device information (1) part number package body size (nom) TIC12400-Q1 tssop (38) 9.70 mm x 4.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic productfolder TIC12400-Q1 voltage regulator gnd 37 38 sw sw vs vs 13 14 25 33 ... in0 in1 in2 in9 34 in10 35 sw sw in11 36 in12 12 in23 ... mcu 19 vdd 24 15 16 17 18 20 23 22 9 28 ep agnd dgnd cap_pre cap_a cap_d /int /cs sclk si so 21 reset mosi miso gpio sclk /cs /int vdd vbat copyright ? 2016, texas instruments incorporated support &community tools & software technical documents ordernow
2 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings ............................................................ 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 6 6.6 timing requirements ............................................. 10 6.7 typical characteristics ............................................ 11 7 parameter measurement information ................ 13 8 detailed description ............................................ 14 8.1 overview ................................................................. 14 8.2 functional block diagram ....................................... 15 8.3 feature description ................................................. 16 8.4 device functional modes ........................................ 29 8.5 programming .......................................................... 45 8.6 register_maps .................................................. 48 8.7 programming guidelines ....................................... 112 9 application and implementation ...................... 115 9.1 application information .......................................... 115 9.2 using TIC12400-Q1 in a 12 v automotive system ................................................................... 115 9.3 resistor-coded switches detection in automotive body control module ............................................. 117 10 power supply recommendations ................... 121 11 layout ................................................................. 122 11.1 layout guidelines ............................................... 122 11.2 layout example .................................................. 123 12 device and documentation support ............... 124 12.1 receiving notification of documentation updates .................................................................. 124 12.2 community resources ........................................ 124 12.3 trademarks ......................................................... 124 12.4 electrostatic discharge caution .......................... 124 12.5 glossary .............................................................. 124 13 mechanical, packaging, and orderable information ......................................................... 125 4 revision history date revision notes august 2017 * initial release.
3 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) i = input, o = output, i/o = input and output, p = power. 5 pin configuration and functions dcp package 38-pin tssop top view pin functions pin type (1) description no. name 1 in13 i/o ground switch monitoring input with current source 2 in14 i/o ground switch monitoring input with current source 3 in15 i/o ground switch monitoring input with current source 4 in16 i/o ground switch monitoring input with current source 5 in17 i/o ground switch monitoring input with current source 6 in18 i/o ground switch monitoring input with current source 7 in19 i/o ground switch monitoring input with current source 8 in20 i/o ground switch monitoring input with current source 9 agnd p ground for analog circuitry 10 in21 i/o ground switch monitoring input with current source 11 in22 i/o ground switch monitoring input with current source 12 in23 i/o ground switch monitoring input with current source 13 in0 i/o ground/v bat switch monitoring input with configurable current sink or source. 14 in1 i/o ground/v bat switch monitoring input with configurable current sink or source. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 in13 in14 in15 in16 in17 in18 in19 in20 agnd in21 in22 in23 in0 in1 /cs sclk si so vdd vsvs in12 in11 in10 in9 in8 in7 in6 in5 dgnd in4 in3 in2 /int cap_d cap_pre reset cap_a 30 29 28 27 26 25 24 23 22 21 20 31 38 37 36 35 34 33 32 exposed pad not to scale
4 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin type (1) description no. name 15 cs i active-low input. chip select from the master for the spi interface. 16 sclk i serial clock output from the master for the spi interface 17 si i serial data input for the spi interface. 18 so o serial data output for the spi interface 19 v dd p 3.3 v to 5.0 v logic supply for the spi communication. the spi i/os are not fail-safe protected: vdd needs to be present during any spi traffic to avoid excessive leakage currents and corrupted spi i/o logic levels. 20 cap_a i/o external capacitor connection for the analog ldo. use capacitance value of 100nf. 21 reset i keep reset low for normal operation and drive reset high and release it to perform a hardware reset of the device. the reset pin is connected to ground via a 1m ? pull-down resistor. if not used, the reset pin shall be grounded to avoid any accidental device reset due to coupled noise onto this pin. 22 cap_pre i/o external capacitor connection for the pre-regulator. use capacitance value of 1 f. 23 cap_d i/o external capacitor connection for the digital ldo. use capacitance value of 100nf. 24 int o open drain output. pulled low (internally) upon change of state on the input or occurrence of a special event. 25 in2 i/o ground/v bat switch monitoring input with configurable current sink or source. 26 in3 i/o ground/v bat switch monitoring input with configurable current sink or source. 27 in4 i/o ground/v bat switch monitoring input with configurable current sink or source. 28 dgnd p ground for digital circuitry 29 in5 i/o ground/v bat switch monitoring input with configurable current sink or source. 30 in6 i/o ground/v bat switch monitoring input with configurable current sink or source. 31 in7 i/o ground/v bat switch monitoring input with configurable current sink or source. 32 in8 i/o ground/v bat switch monitoring input with configurable current sink or source. 33 in9 i/o ground/v bat switch monitoring input with configurable current sink or source. 34 in10 i/o ground switch monitoring input with current source 35 in11 i/o ground switch monitoring input with current source 36 in12 i/o ground switch monitoring input with current source 37 v s p power supply input pin. 38 v s p power supply input pin. --- ep p exposed pad. the exposed pad is not electrically connected to agnd or dgnd. connect ep to the board ground to achieve rated thermal and esd performance.
5 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) tested for load dump and jump start conditions with nominal operating voltage no greater than 16v for the life of a 12-v automotive system. refer to using TIC12400-Q1 in a 12 v automotive system for more details. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit input voltage v s , int -0.3 40 (2) v v dd , sclk, si, so, cs, reset -0.3 6 v in0- in23 -24 40 (2) v cap_pre -0.3 5.5 v cap_a -0.3 5.5 v cap_d -0.3 2 v operating junction temperature, t j -40 150 c storage temperature, t stg -55 155 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. (2) 4kv rating on pins in0-in23 are stressed with respect to gnd (with agnd, dgnd, and ep tied together). 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) all pins 2000 v pins in0-in23 (2) 4000 charged-device model (cdm), per aec q100-011 all pins 500 corner pins (pin 1, 19, 20 and 38) 750 contact discharge, un-powered, per iso- 10605: ? external components: capacitor = 15 nf; resistor = 10 ? esd generator parameters: storage capacitance = 150 pf; discharge resistance = 330 or 2000 pins in0-in23 8000 contact discharge, powered-up, per iso- 10605: ? external components: capacitor = 15 nf; resistor = 33 ? esd generator parameters: storage capacitance = 150 pf or 330pf; discharge resistance = 330 or 2000 pins in0-in23 8000 (1) tested for load dump and jump start conditions with nominal operating voltage no greater than 16 v for the life of a 12-v automotive system. refer to using TIC12400-Q1 in a 12 v automotive system for more details. (2) lowest frequency characterized. 6.3 recommended operating conditions over operating free-air temperature range and v s = 12 v (unless otherwise noted) min nom max unit v s power supply voltage 4.5 35 (1) v v dd logic supply voltage 3.0 5.5 v v /int int pin voltage 0 35 (1) v v inx in0 to in23 input voltage 0 35 (1) v v reset reset pin voltage 0 5.5 v v spi_io spi input/output logic level 0 v dd v f spi spi communication frequency 20 (2) 4m hz t a operating free-air temperature -40 125 c
6 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) TIC12400-Q1 unit dcp (tssop) 38 pins r ja junction-to-ambient thermal resistance 33.6 c/w r jc(top) junction-to-case (top) thermal resistance 18.4 c/w r jb junction-to-board thermal resistance 15.2 c/w jt junction-to-top characterization parameter 0.5 c/w jb junction-to-board characterization parameter 15.0 c/w r jc(bot) junction-to-case (bottom) thermal resistance 1.2 c/w (1) verified by design. 6.5 electrical characteristics over operating free-air temperature range, v s = 4.5 v to 35 v, and v dd = 3 v to 5.5 v (unless otherwise noted) parameter test conditions min typ max unit power supply i s_cont continuous mode v s power supply current continuous mode, i wett = 10 ma, all switches open, no active adc conversion or comparator comparison, no unserviced interrupt 5.6 7 ma i s_poll_comp_25 polling mode v s power supply average current in comparator mode t a = 25 polling mode, t poll = 64 ms, t poll _act= 128 s, all 24 channels active and configured to comparator mode, all switches open, i wett = 10 ma, no unserviced interrupt 68 100 a i s_poll_comp_85 t a = -40 to 85 c 68 110 a i s_poll_comp t a = -40 to 125 c 68 170 a i s_poll_adc_25 polling mode v s power supply average current in adc mode t a = 25 polling mode, t poll = 64 ms, t poll_act = 128 s, all 24 channels active and configured to adc mode, all switches open, i wett = 10 ma, no unserviced interrupt 75 105 a i s_poll_adc_85 t a = -40 to 85 c 75 120 a i s_poll_adc t a = -40 to 125 c 75 180 a i s_reset reset mode v s power supply current reset mode, v reset = v dd . v s = 12 v, all switches open, t a =25 c 12 17 a i s_idle_25 v s power supply average current in idle state trigger bit in config register = logic 0, t a = 25 c, no unserviced interrupt 50 75 a i s_idle_85 trigger bit in config register = logic 0, t a = -40 c to 85 c, no unserviced interrupt 50 95 a i s_idle trigger bit in config register = logic 0, t a = -40 c to 125 c, no unserviced interrupt 50 145 a i dd logic supply current from v dd sclk = si = 0 v, cs = int = v dd , no spi communication 1.5 10 a v por_r power on reset (por) voltage for v s threshold for rising v s from device off condition resulting in int pin assertion and a flagged por bit in the int_stat register 3.85 4.5 v v por_f threshold for falling v s from device normal operation to reset mode and loss of spi communication 1.95 2.8 v v ov_r over-voltage (ov) condition for v s threshold for rising v s from device normal operation resulting in int pin assertion and a flagged ov bit in the int_stat register 35 40 v v ov_hyst over-voltage (ov) condition hysteresis for v s 1 3.5 v v uv_r under-voltage (uv) condition for v s threshold for rising v s from under-voltage condition resulting in int pin assertion and a flagged uv bit in the int_stat register 3.85 4.5 v v uv_f threshold for falling v s from under-votlage condition resulting in int pin assertion and a flagged uv bit in the int_stat register 3.7 4.4 v v uv_hyst under-voltage (uv) condition hysteresis for v s (1) 75 275 mv v dd_f threshold for falling v dd resulting in loss of spi communication 2.5 2.9 v v dd_hyst valid v dd voltage hysteresis 50 150 mv wetting current accuracy (digital switches, maximum resistance value with switch closed 100 ? , minimum resistance value with switch open 5000 ? )
7 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range, v s = 4.5 v to 35 v, and v dd = 3 v to 5.5 v (unless otherwise noted) parameter test conditions min typ max unit i wett (cso) wetting current accuracy for cso (switch closed) 1 ma setting 4.5 v v s 35 v 0.84 1 1.14 ma 2 ma setting 1.71 2 2.32 5 ma setting 4.5 v v s < 5 v 2.39 5.5 5 v v s 35 v 4.3 5 5.6 10 ma setting 4.5 v v s < 6 v 2.4 11 6 v v s 35 v 8.4 10 11.4 15 ma setting 4.5 v v s < 6.5 v 2.4 16.5 6.5 v v s 35 v 12.5 15 17 i wett (csi) wetting current accuracy for csi (switch closed) 1 ma setting 4.5 v v s 35v 0.75 1.1 2.05 ma 2 ma setting 1.6 2.2 3.3 5 ma setting 4.3 5.6 7.1 10 ma setting 9.2 11.5 13.4 15 ma setting 4.5 v v s < 6.0v 11 16.5 19.2 6 v v s 35v 13.7 16.5 19.2 v csi_drop_open voltage drop from in x pin to agnd across csi (switch open) 10 ma setting, r sw = 5k ? 4.5 v v s 35v 1.7 v 15 ma setting, r sw = 5k ? 1.7 v csi_drop_closed voltage drop from inx pin to ground across csi (switch closed) 2ma setting, i in = 1ma (4.5v vs 35v) 4.5 v v s 35v 1.2 v 5ma setting, i in = 1ma or 2ma 1.3 v 10ma setting, i in = 1ma, 2ma, or 5ma 1.5 v 15ma setting, i in = 1ma, 2ma, 5ma, or 10ma 2.1 v wetting current accuracy (analog switches) i wett wetting current accuracy 1 ma setting 4.5 v v s 35 v, v s - inx 2.5 v 0.84 1 1.14 ma 2 ma setting 1.71 2 2.32 5 ma setting 5.5 v v s 35 v, v s - inx 2.5 v 4.3 5 5.6 10 ma setting 6 v v s 35 v, v s - inx 4 v 8.4 10 11.4 15 ma setting 6.5 v v s 35 v, v s - inx 5 v 12.5 15 17 leakage currents i in_leak_off leakage current at input inx when channel is disabled 0 v v inx v s , channel disabled (en_inx register bit= logic 0) -4 5.3 a i in_leak_off_25 0 v v inx v s , channel disabled (en_inx register bit= logic 0), t a = 25 c -0.5 0.5 i in_leak_0ma leakage current at input inx when wetting current setting is 0ma 0 v v inx 6 v, 6 v v s 35 v , i wett setting = 0 ma -110 110 a a i in_leak_loss_of_gnd leakage current at input inx under loss of gnd condition v s = 24 v, 0 v v inx 24 v, all grounds (agnd, dgnd, and ep) = 24 v, v dd shorted to the grounds (1) -5 a i in_leak_loss_of_vs leakage current at input inx under loss of v s condition 0 v v inx 24 v, v s shorted to the grounds = 0 v, v dd = 0 v 5 a logic levels v /int_l int output low voltage i /int = 2 ma 0.35 v i /int = 4 ma 0.6 v so_l so output low voltage i so = 2 ma 0.2v dd v v so_h so output high voltage i so = -2 ma 0.8v dd v
8 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range, v s = 4.5 v to 35 v, and v dd = 3 v to 5.5 v (unless otherwise noted) parameter test conditions min typ max unit v in_l si, sclk, and cs input low voltage 0.3v dd v 1v in_h si, sclk, and cs input high voltage 0.7v dd v v reset_l reset input low voltage 0.8 v v reset_h reset input high voltage 1.6 v r reset_25 reset pin internal pull-down resistor v reset = 0 to 5.5v, t a =25 c 0.85 1.25 1.7 m ? r reset v reset = 0 to 5.5v, t a = ? 40 to 125 c 0.2 2.1 switch input and v s measurement conversion parameters res resolution 10 bits 1out sw switch input conversion output 1ma setting 4.5 v v s 35 v, 100 ? resistance to ground at inx 12 17 26 lsb 4.5 v v s 35 v, 300 ? resistance to ground at inx 42 51 64 4.5 v v s 35 v, 600 ? resistance to ground at inx 87 102 122 2ma setting 4.5 v v s 35 v, 100 ? resistance to ground at inx 28 34 45 lsb 4.5 v v s 35 v, 300 ? resistance to ground at inx 89 102 122 4.5 v v s 35 v, 600 ? resistance to ground at inx 181 205 236 5ma setting 5 v v s 35 v, 100 ? resistance to ground at inx 72 85 105 lsb 5 v v s 35 v, 300 ? resistance to ground at inx 223 256 296 5 v v s 35 v, 600 ? resistance to ground at inx 393 512 620 10ma setting 6 v v s 35 v, 100 ? resistance to ground at inx 142 171 202 lsb 6 v v s 35 v, 250 ? resistance to ground at inx 333 427 486 6 v v s 35 v, 400 ? resistance to ground at inx 430 683 823 15ma setting 6.5 v v s 35 v, 100 ? resistance to ground at inx 166 256 301 lsb 6.5 v v s 35 v, 200 ? resistance to ground at inx 325 512 582 6.5 v v s 35 v, 300 ? resistance to ground at inx 450 768 879 out vs v s measurement output tolerance to full-scale range v s measurements (v s 4.5v), vs_ratio= 0 in register config 2% v s measurements (v s 4.5v), vs_ratio= 1 in register config 2% v fsr input full-scale range inx measurements 6 v v s measurements (v s 4.5v), vs_ratio= 0 in register config 9 v s measurements (v s 4.5v), vs_ratio= 1 in register config 30 r in, sc input resistance inx measurements 240 k ? r ratio input voltage divider factor (1) inx measurements 2 - v s measurements (v s 4.5 v), vs_ratio = 0 in register config 3 - v s measurements (v s 4.5 v), vs_ratio = 1 in register config 10 -
9 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating free-air temperature range, v s = 4.5 v to 35 v, and v dd = 3 v to 5.5 v (unless otherwise noted) parameter test conditions min typ max unit comparator parameters v th_ comp_2v comparator threshold for 2 v thres_comp = 2 v 1.85 2.25 v v th_ comp_2p7v comparator threshold for 2.7 v thres_comp = 2.7 v 2.4 2.9 v v th_ comp_3v comparator threshold for 3 v thres_comp = 3 v 2.85 3.3 v v th_ comp_4v comparator threshold for 4 v thres_comp = 4 v 3.7 4.35 v v s_comp minimum v s requirement for proper detection thres_comp = 2 v 4.5 v thres_comp = 2.7 v 5.0 thres_comp = 3 v 5.5 thres_comp = 4 v 6.5 r in, comp comparator equivalent input resistance thres_comp = 2 v 30 130 k ? thres_comp = 2.7 v 35 130 thres_comp = 3 v 35 105 thres_comp = 4 v 43 95
10 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) if there is a pending interrupt (/int pin asserted low), it can take up to 1ms for the device to complete the reset. 6.6 timing requirements v s = 4.5 v to 35 v, v dd = 3 v to 5.5 v, and 10 pf capacitive load on so unless otherwise noted; verified by design and characterization parameter test condition min nom max unit switch monitoring, interrupt, startup and reset t poll_act polling active time accuracy polling mode -12% 12% t poll_act _m polling active time accuracy for matrix inputs polling mode with matrix enabled -12% 12% t poll polling time accuracy polling mode -12% 12% t comp comparator detection time 18 s t adc adc conversion time sample and hold time included 24 s t ccp_tran transition time between last input sampling and start of clean current 20 s t ccp_act clean current active time -12% 12% t startup polling startup time 200 300 400 s t int_activ e active int assertion duration 1.5 2 2.5 ms t int_inact ive int de-assertion duration during a pending interrupt 3 4 5 ms t int_idle interrupt idle time 80 100 120 s t reset time required to keep the reset pin high to successfully reset the device (no pending interrupt) (1) 2 s t react delay between a fault event (ov, uv, tw, or tsd) to a high to low transition on the int pin see figure 13 for ov example. 20 s spi interface t lead falling edge of cs to rising edge of sclk setup time 100 ns t lag falling edge of sclk to rising edge of cs setup time 100 ns t su si to sclk falling edge setup time 30 ns t hold si hold time after falling edge of sclk 20 ns t valid time from rising edge of sclk to valid so data 70 ns t so(en) time from falling edge of cs to so low-impedance 60 ns t so(dis) time from rising edge of cs to so high-impedance loading of 1 k ? to gnd. see figure 14 . 60 ns t r si, cs, and sclk signals rise time 5 30 ns t f si, cs, and sclk signals fall time 5 30 ns t inter_fr ame delay between two spi communication ( cs low) sequences 1.5 s t ckh sclk high time 120 ns t ckl sclk low time 120 ns t initiation delay between valid v dd voltage and initial spi communication 45 s
11 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.7 typical characteristics t a = 25 c figure 1. wetting current output - cso vs. v s voltage v s = 12 v figure 2. wetting current output - cso vs. temperature t a = 25 c figure 3. comparator threshold vs. v s voltage i (wett) = 1 ma 4.5 v v s 35 v figure 4. adc code vs. equivalent input resistance i (wett) = 2 ma 4.5 v v s 35 v figure 5. adc code vs. equivalent input resistance i (wett) = 5 ma 4.5 v v s 5 v figure 6. adc code vs. equivalent input resistance temperature (c) wetting current output- cso (ma) -40 -20 0 20 40 60 80 100 120 140 160 0 2 4 6 8 10 12 14 16 d001 i wett =1ma i wett =2ma i wett =5ma i wett =10ma i wett =15ma v s voltage (v) comparator threshold (v) 0 5 10 15 20 25 30 35 40 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 d001 thres_comp=2v thres_comp=2.7v thres_comp=3v thres_comp=4v v s voltage (v) wetting current output- cso (ma) 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 18 d001 i wett =1ma i wett =2ma i wett =5ma i wett =10ma i wett =15ma equivalent input resistance ( : ) adc code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 200 400 600 800 1000 1200 d001adc_ adc code min adc code max equivalent input resistance ( : ) adc code 5 505 1005 1505 2005 2505 3005 3505 4005 4505 5000 0 200 400 600 800 1000 d001plotadc_ adc code min adc code max equivalent input resistance ( : ) adc code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 100 200 300 400 500 600 700 d001adc_ adc code min adc code max
12 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) i (wett) = 5 ma 4.5 v v s 35 v figure 7. adc code vs. equivalent input resistance i (wett) = 10 ma 4.5 v v s 6 v figure 8. adc code vs. equivalent input resistance i (wett) = 10 ma 6 v v s 35 v figure 9. adc code vs. equivalent input resistance i (wett) = 15 ma 4.5 v v s 6.5 v figure 10. adc code vs. equivalent input resistance i (wett) = 15 ma 6.5 v v s 35 v figure 11. adc code vs. equivalent input resistance equivalent input resistance ( : ) adc code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 100 200 300 400 500 600 700 800 900 1000 1100 d001adc_ adc code min adc code max equivalent input resistance ( : ) adc code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 100 200 300 400 500 600 700 800 900 d001adc_ adc code min adc code max equivalent input resistance ( : ) adc code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 100 200 300 400 500 600 700 800 900 1000 1100 d001adc_ adc code min adc code max equivalent input resistance ( : ) adc code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 100 200 300 400 500 600 700 800 900 d001adc_ adc code min adc code max equivalent input resistance ( : ) adc code 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 100 200 300 400 500 600 700 800 900 1000 1100 d001adc_ adc code min adc code max
13 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 parameter measurement information figure 12. spi timing parameters figure 13. t react timing parameters figure 14. t so(dis) timing parameters /cs sclk v dd t t lead t si t initiation t so(en) so t t ckh t t t ckl t t hold t t su t t valid t t lag t t interframe t so(dis) /int v s v ov_r v /int_l t react v in_h v so_h t so(dis) so /cs 1k gnd so
14 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the TIC12400-Q1 is an advanced 24-input multiple switch detection interface (msdi) device designed to detect external mechanical switch status in a 12-v automotive system by acting as an interface between the switches and the low-voltage microcontroller. the TIC12400-Q1 is an integrated solution that replaces many discrete components and provides integrated protection, input serialization, and system wake-up capability. the device monitors 14 switches to gnd and 10 additional switches that can be programmed to be connected to either gnd or v bat . it features spi interface to report individual switch status and provides programmability to control the device operation. the TIC12400-Q1 features a 10-bit adc which is useful to monitor analog inputs such as resistor coded switches that have multiple switching positions. to monitor only digital switches, an integrated comparator can be used instead to monitor the input status. the device has 2 modes of operation: continuous mode and polling mode. the polling mode is a low-power mode that can be activated to reduce current drawn in the system by only turning on the wetting current for a small duty cycle to detect switch status changes. an interrupt is generated upon detection of switch status change and it can be used to wake up the microcontroller to bring the entire system back to operation.
15 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2 functional block diagram 1ma to 15ma or off 1ma to 15ma or off v s esd protection 1ma to 15ma or off v s esd protection sw sw r1 r2 mux r5 r6 + adc + state machine registers digital block input/ output buffer control logic pre-regulator analog ldo digital ldo power management oscillator v dig sw sw v s r3 r4 sw + v test 1ma to 15ma or off 1ma to 15ma or off v s esd protection sw 1ma to 15ma or off v s esd protection sw ... ... under-voltage protection over-voltage protection over-temperature protection 1 0? 13 14 25 26 34 12 37 38 33 sw copyright ? 2016, texas instruments incorporated agnd agnd agnd agnd agnd agnd agnd dgnd agnd 9 28 19 15 16 17 18 21 22 20 23 dgnd agnd agnd 35 36 1 agnd v s v s cap_pre cap_a cap_d /int v dd /cs sclk si so reset agnd dgnd in23 in13 in10 in11 in12 ... in9 in0 in1 in2 in3 agnd 24
16 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3 feature description 8.3.1 v s pin the v s supply provides power to the entire chip and it is designed to be connected directly to a 12-v automotive battery via a reverse-polarity blocking diode. 8.3.2 v dd pin the v dd supply is used to determine the logic level on the spi communication interface, source the current for the so driver, and sets the pull-up voltage for the cs pin. it can also be used as a possible external pull-up supply for the int pin in addition to the v s and it shall be connected to a 3 v to 5.5-v logic supply. removing v dd from the device disables spi communications but does not reset the register configurations. 8.3.3 device initialization when the device is powered up for the first time, the condition is called power-on reset (por), which sets the registers to their default values and initializes the device state machine. the internal por controller holds the device in a reset condition until v s has reached v por_r , at which the reset condition is released with the device registers and state machine initialized to their default values. after the initialization process is completed, the int pin is asserted low to notify the microcontroller, and the register bit por in the int_stat register is asserted to logic 1. the spi flag bit por is also asserted at the spi output (so). during device initialization, factory settings are programmed into the device to allow accurate device operation. the device performs a self-check after the device is programmed to ensure correct settings are loaded. if the self-check returns an error, the chk_fail bit in the int_stat register will be flagged to logic 1 along with the por bit. if this event occurs the microcontroller is recommended to initiate software reset (see section software reset ) to re-initialize the device to allow the correct settings to be re-programmed. 8.3.4 device trigger after device initialization, the TIC12400-Q1 is ready to be configured. the microcontroller can use spi commands to program desired settings to the configuration registers. once the device configuration is completed, the microcontroller is required to set the bit trigger in the config register to logic 1 in order to activate wetting current and start external switch monitoring. after switch monitoring initiates, the configuration registers turn into read-only registers (with the exception of the trigger, crc_t, and reset bits in the config register and all bits in the ccp_cfg1 register). if at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit trigger in the config register to logic 0 to stop wetting current and switch monitoring. the microcontroller can then program configuration registers to the desired settings. once the re-configuration is completed the microcontroller can set the trigger bit back to logic 1 to re-start switch monitoring. note the cyclic redundancy check (crc) feature stays accessible when trigger bit is in logic 1, allowing the microcontroller to verify device settings at all time. refer to section cyclic redundancy check (crc) for more details of the crc feature. 8.3.5 device reset there are 3 ways to reset the TIC12400-Q1 and re-initialize all registers to their default values: 8.3.5.1 v s supply por the device is turned off and all register contents are lost if the v s voltage drops below v por_f . to turn the device back on, the v s voltage must be raised back above v por_r , as illustrated in figure 15 . the device then starts the initialization process as described in section device initialization .
17 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 15. v s is lowered below the por threshold, then ramped back up to complete a por cycle 8.3.5.2 hardware reset microcontroller can toggle the reset pin to perform a hardware reset to the device. the reset pin is internally pulled-down via a resistor (1.25m ? typical) and must be kept low for normal operation. when the reset pin is toggled high, the device enters the reset state with most of the internal blocks turned off and consumes very little current of i s_reset . switch monitoring and spi communications are stopped in the reset state, and all register contents are cleared. when reset pin is toggled back low, all the registers are set to their default values and the device state machine is re-initialized, similar to a por event. when the re-initialization process is completed the int pin is asserted low, and the interrupt register bit por and the spi status flag por are both asserted to notify the microcontroller that the device has completed the reset process. note in order to successfully reset the device, the reset pin needs to be kept high for a minimum duration of t reset . the pin is required to be driven with a stable input (below v reset_l for logic low or above v reset_h for logic h) to prevent the device from accidental reset. 8.3.5.3 software reset in addition to hardware reset the microcontroller can also issue a spi command to initiate software reset. software reset is triggered by setting the reset bit in the register config to logic 1, which re-initializes the device with all registers set to their default values. once the re-initialization process is completed, the int pin is asserted low, and the interrupt register bit por and the spi status flag por are both asserted to notify the microcontroller that the device has completed the reset process. 8.3.6 v s under-voltage (uv) condition during normal operation of a typical 12v automotive system, the v s voltage is usually quite stable and stays well above 11 v. however, the v s voltage might drop temporarily during certain vehicle operations, such as cold cranking. if the v s voltage drops below v uv_f , the TIC12400-Q1 enters the under-voltage (uv) condition since there is not enough voltage headroom for the device to accurately generate wetting currents. the following describes the behavior of the TIC12400-Q1 under uv condition: 1. all current sources/sinks de-activate and switch monitoring stops. 2. interrupt is generated by asserting the int pin low and the bit uv in the interrupt register (int_stat) is flagged to logic 1. the bit uv_stat is asserted to logic 1 in the register in_stat_misc. the oi spi flag is asserted during any spi transactions. the int pin is released and the interrupt register (int_stat) is cleared on the rising edge of cs provided that the interrupt register has been read during the spi transaction. 3. spi communication stays active, and all register settings stay intact without resetting. previous switch status, if needed, can be retrieved without interruption. 4. the device continues to monitor the v s voltage, and the uv condition sustains if the v s voltage continues to stay below v uv_r . no further interrupt is generated once cleared. v s v por_r v por_f device off normal operation device off normal operation time
18 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) note the device resets as described in section vs supply por if the v s voltage drops below v por_f . when the v s voltage rises above v uv_r , the int pin is asserted low to notify the microcontroller that the uv condition no longer exists. the uv bit in the register int_stat is flagged to logic 1 and the bit uv_stat bit is de-asserted to logic 0 in the register in_stat_misc to reflect the clearance of the uv condition. the device resumes operation using current register settings (regardless of the int pin and spi communication status) with polling restarted from the first enabled channel. the switch state change (ssc) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline switch status for subsequent polling cycles. the content of the int_stat register, once read by the microcontroller, is cleared, and the int pin is released afterwards. the following diagram describes the TIC12400-Q1 operation at various different v s voltages. if the v s voltage stays above v uv_f (case 1), the device stays in normal operation. if the v s voltage drops below v uv_f but stays above v por_f (case 2), the device enters the uv condition. if v s voltage drops below v por_f (case 3), the device resets and all register settings are cleared. the microcontroller is then required to re-program all the configuration registers in order to resume normal operation after the v s voltage recovers. figure 16. TIC12400-Q1 operation at various v s voltage levels 8.3.7 v s over-voltage (ov) condition if v s voltage rises above v ov_r , the TIC12400-Q1 enters the over-voltage (ov) condition to prevent damage to internal structures of the device on the v s and inx (for battery-connected switches) pins. the following describes the behavior of the TIC12400-Q1 under ov condition: 1. all current sources/sinks de-activate and switch monitoring stops. 2. interrupt is generated by asserting the int pin low and the bit ov in the interrupt register (int_stat) is flagged to logic 1. the bit ov_stat is asserted to logic 1 in the register in_stat_misc. the oi spi flag is asserted during any spi transactions. the int pin is released and the interrupt register (int_stat) is cleared on the rising edge of cs provided that the interrupt register has been read during the spi transaction. 3. spi communication stays active, and all register settings stay intact without resetting. previous switch status, if needed, can be retrieved without any interruption. 4. the device continues to monitor the v s voltage, and the ov condition sustains if the v s voltage continues to stay above v ov_r - v ov_hyst . no further interrupt is generated once cleared. when the v s voltage drops below v ov_r - v ov_hyst , the int pin is asserted low to notify the microcontroller that the over-voltage condition no longer exists. the ov bit in the register int_stat is flagged to logic 1 and the bit ov_stat bit is de-asserted to logic 0 in the register in_stat_misc to reflect the clearance of the ov condition. the device resumes operation using current register settings (regardless of the int pin and spi communication status) with polling restarted from the first enabled channel. the switch state change (ssc) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline status for subsequent polling cycles. the content of the int_stat register, once read by the microcontroller, is cleared and the int pin is released afterwards. v s v por_r v por_f device off time v uv_f case 1 case 2 case 3 t cranking t
19 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 8.3.8 switch inputs settings in0 to in23 are inputs connected to external mechanical switches. the switch status of each input, whether open or closed, is indicated by the status registers. table 1 below describes various settings that can be configured for each input. note some settings are shared between multiple inputs. it is required to first stop device operation by setting the trigger bit low in the register config before making any configuration changes, as described in device trigger . table 1. TIC12400-Q1 wetting current and threshold setting details input threshold wetting current current source (cso) / current sink (csi) supported switch type comparator input mode adc input mode in0 thres_comp_in 0_in3 thres0 to thres7 thres_com wc_in0_in1 cso csi switch to gnd switch to vbat in1 thres0 to thres7 cso csi switch to gnd switch to vbat in2 thres0 to thres7 wc_in2_in3 cso csi switch to gnd switch to vbat in3 thres0 to thres7 cso csi switch to gnd switch to vbat in4 thres_comp_in 4_in7 thres0 to thres7 wc_in4 cso csi switch to gnd switch to vbat in5 thres0 to thres7 wc_in5 cso csi switch to gnd switch to vbat in6 thres0 to thres7 wc_in6_in7 cso csi switch to gnd switch to vbat in7 thres0 to thres7 cso csi switch to gnd switch to vbat in8 thres_comp_in 8_in11 thres0 to thres7 wc_in8_in9 cso csi switch to gnd switch to vbat in9 thres0 to thres7 cso csi switch to gnd switch to vbat in10 thres0 to thres7 wc_in10 cso switch to gnd in11 thres0 to thres7 wc_in11 cso switch to gnd in12 thres_comp_in 12_in15 thres2a thres2b wc_in12_13 cso switch to gnd in13 thres2a thres2b cso switch to gnd in14 thres2a thres2b wc_in14_15 cso switch to gnd in15 thres2a thres2b cso switch to gnd in16 thres_comp_in 16_in19 thres2a thres2b wc_in16_17 cso switch to gnd in17 thres2a thres2b cso switch to gnd in18 thres3a thres3b thres3c wc_in18_19 cso switch to gnd in19 thres3a thres3b thres3c cso switch to gnd
20 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) table 1. TIC12400-Q1 wetting current and threshold setting details (continued) input threshold wetting current current source (cso) / current sink (csi) supported switch type comparator input mode adc input mode in20 thres_comp_in 20_in23 thres3a thres3b thres3c wc_in20_21 cso switch to gnd in21 thres3a thres3b thres3c cso switch to gnd in22 thres3a thres3b thres3c wc_in22 cso switch to gnd in23 thres3a thres3b thres3c thres8 thres9 wc_in23 cso switch to gnd 8.3.8.1 input current source/sink selection among the 24 inputs, in10 to in23 are intended for monitoring only ground-connected switches and are connected to current sources. in0 to in9 can be programmed to monitor either ground-connected switches or battery-connected switches by configuring the cs_select register. the default configuration of the in0-in9 inputs after por is to monitor ground-connected switches (current sources are selected). to set an input to monitor battery-connected switches, set the corresponding bit to logic 1. 8.3.8.2 input mode selection the TIC12400-Q1 has a built-in adc and a comparator that can be used to monitor resistor coded switches or digital switches. digital switch inputs have only two states, either open or closed, and can be adequately detected by a comparator. resistor coded switches may have multiple positions that need to be detected and an adc is appropriate to monitor the different states. each input of the TIC12400-Q1 can be individually programmed to use either a comparator or an adc by configuring the appropriate bits in the mode register depending on the knowledge of the external switch connections. the benefit of using a comparator instead of an adc to monitor digital switches is its reduced polling time which translates to overall power saving when the device operates in the low-power polling mode. comparator input mode is selected by default for all enabled inputs upon device reset. 8.3.8.3 input enable selection the TIC12400-Q1 provides switch status monitoring for up to 24 inputs, but there might be circumstances in which not all inputs need to be constantly monitored. the microcontroller may choose to enable/disable monitoring of certain inputs by configuring the in_en register. setting the corresponding bit to logic 0 de- activates the wetting current source/sink and stops switch status monitoring for the input. disabling monitoring of unused inputs reduces overall power consumption of the device. all inputs are disabled by default upon device reset.
21 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.8.4 thresholds adjustment when an input is configured as comparator input mode, the threshold level for interrupt generation can be programmed by setting the thres_comp register. the threshold level settings can be set for each individual input groups and each group consists of 4 inputs. four threshold levels are available: 2v, 2.7v, 3v, and 4v. when an input is configured as adc input mode the threshold level for interrupt generation can be configured up to 1023 different levels by setting the thres_cfg1 to thres_cfg2 registers. one threshold level can be programmed individually for each of the inputs from in0 to in11. additionally, one common threshold, shared between inputs in0 to in11, can be programmed by configuring the thres_com bits in register matrix . the common threshold acts independently from the threshold thres0 to thres7. inputs in12 to in17 use 2 preset threshold levels (thres2a and thres2b). inputs 18 to 22 use 3 preset threshold levels (thres3a, thres3b, and thres3c). input 23 uses 5 preset threshold levels (thres3a, thres3b, thres3c, thres8 and thres9). when multiple threshold settings are used for adc inputs, the thresholds levels need to be configured properly. use the rules below (see table 2 ) when setting up the threshold levels: table 2. proper threshold configuration for adc inputs input proper threshold configuration in12 to in17 thres2b thres2a in18 to in22 thres3c thres3b thres3a in23 thres9 thres8 thres3c thres3b thres3a caution should be used when setting up the threshold for switches that are connected externally to the battery as there is a finite voltage drop (as high as v csi_drop_open for 10ma and 15ma settings) across the current sinks. therefore, even for an open switch, then voltage on the inx pin can be as high as v csi_drop_open and the detection threshold shall be configured above it. it shall also be noted that a lower wetting current sink setting might not be strong enough to pull the inx pin close to ground in the presence of a leaky open external switch, as illustrated in the diagram below (see figure 17 ). in this example, the external switch, although in the open state, has large leakage current and can be modelled as an equivalent resistor (r dirt ) of 5k ? . the 2ma current sink is only able to pull the inx pin voltage down to 4v, even if the switch is in the open state. figure 17. example showing the calculation of the inx pin voltage for a leaky battery-connected switch it is possible to configure an input to adc input mode, instead of comparator input mode, to monitor single- threshold digital switches. the following programming procedure is recommended under such configuration: v bat battery- connected switch + r dirt r sw sw gnd inx gnd TIC12400-Q1 2ma 5 n? open 14v
22 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 3. recommended threshold configuration when using an adc input to monitor digital switches input recommended threshold configuration in0 to in11 configure the desired threshold to one of the settings from thres0 to thres7 and map it accordingly in12 to in17 ? configure the desired threshold to thres2b ? set thres2a to the same code as thres2b ? disable interrupt generation for thres2a by configuring the int_en_cfg1 or int_en_cfg2 register. in18 to in22 ? configure the desired threshold to thres3c ? set thres3a and thres3b to the same code as thres3c. ? disable interrupt generation for thres3a and thres3b by configuring the int_en_cfg3 or int_en_cfg4 register. in23 ? configure the desired threshold to thres9 ? set thres3a, thres3b, thres3c, and thres8 to the same code as thres9. ? disable interrupt generation for thres3a, thres3b, thres3c, and thres8 by configuring the int_en_cfg4 register. 8.3.8.5 wetting current configuration there are 6 different wetting current settings (0ma, 1ma, 2ma, 5ma, 10ma, and 15ma) that can be programmed by configuring the wc_cfg0 and wc_cfg1 registers. 0ma is selected by default upon device reset. to monitor resistor coded switches, a lower wetting current setting (1 ma, 2 ma, or 5 ma) is generally desirable to get the resolution needed to resolve different input voltages while keeping them within the adc full-scale range (0 v to 6 v). higher wetting current settings (10ma and 15ma) are useful to clean switch contact oxidation that may form on the surface of an open switch contact. if switch contact cleaning is required for resistor coded switches, the clean current polling (ccp) feature (refer to section clean current polling (ccp) ) can be activated to generate short cleaning pulses periodically using higher wetting current settings at the end of every polling cycle. the accuracy of the wetting current has stronger dependency on the v s voltage when v s voltage is low. the lower the v s voltage falls, the more deviation on the wetting currents from their nominal values. refer to i wett (cso) and i wett (csi) specifications for more details. 8.3.9 interrupt generation and int assertion the int pin is an active-low, open-drain output that asserts low when an event (switch input state change, temperature warning, over-voltage shutdown ? etc) is detected by the TIC12400-Q1. an external pull-up resistor to v dd is needed on the int pin (see figure 18 ). the int pin can also be connected directly to a 12-v automotive battery to support the microcontroller wake-up feature, as describe in section microcontroller wake- up . figure 18. int connection example #1 TIC12400-Q1 agnd 10k gnd microcontroller v dd /int agnd gnd gpi v dd
23 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.9.1 int pin assertion scheme TIC12400-Q1 supports two configurable schemes for int assertion: static and dynamic. the scheme can be adjusted by configuring the int_config bit in the config register. if the static int assertion scheme is used (int_config = 0 in the config register), the int pin is asserted low upon occurrence of an event. the int pin is released on the rising edge of cs only if a read command has been issued to read the int_stat register while cs is low, otherwise the int will be kept low indefinitely. the content of the int_stat interrupt register is latched on the first rising edge of sclk after cs goes low for every spi transaction, and the content is cleared upon a read command issued to the int_stat register, as illustrated in figure 19 . figure 19. static int assertion scheme in some system implementations an edge-triggered based microcontroller might potentially miss the int assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking up. to prevent missed int assertion and improve robustness of the interrupt behavior, the TIC12400-Q1 provides the option to use the dynamic assertion scheme for the int pin. when the dynamic scheme is used (int_config= 1 in the config register), the int pin is asserted low for a duration of t int_active and is de- asserted back to high if the int_stat register has not been read after t int_active has elapsed. the int is kept high for a duration of t int_inactive , and is re-asserted low after t int_inactive has elapsed. the int pin continues to toggle until the int_stat register is read. if the int_stat register is read when int pin is asserted low, the int pin is released on the read command ? s cs rising edge and the content of the int_stat register is also cleared, as shown in figure 20 . if the int_stat register is read when int pin is de-asserted, the content of the int_stat register is cleared on the read command ? s cs rising edge, and the int pin is not re-asserted back low, as shown in figure 21 . figure 20. dynamic int assertion scheme with int_stat register read during t int_active /cs /int event occurance register read (int_stat register) t int_active t t int_inactive t x int_stat register content cleared x /int pin released /cs /int event occurance register read (non- int_stat register) register read (int_stat register) x int_stat register content cleared x /int pin released
24 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 21. dynamic int assertion scheme with int_stat register read during t int_inactive the static int assertion scheme is selected by default upon device reset. the int pin assertion scheme can only be changed when bit trigger is logic 0 in the config register. 8.3.9.2 interrupt idle time (t int_idle ) time interrupt idle time (t int_idle ) is implemented in TIC12400-Q1 to: ? allow the int pin enough time to be pulled back high by the external pull-up resistor and allow the next assertion to be detectable by an edge-triggered microcontroller. ? minimize the chance of glitching on the int pin if back-to-back events occur. when there is a pending interrupt event and the interrupt event is not masked, t int_idle is applied after the read command is issued to the int_stat register. if another event occurs during the interrupt idle time the int_stat register content is updated instantly but the int pin is not asserted low until t int_idle has elapsed. if another read command is issued to the int_stat register during t int_idle , the int_stat register content is cleared immediately, but the int pin is not re-asserted back low after t int_idle has elapsed. an example of the interrupt idle time is given below to illustrate the int pin behavior under the static int assertion schemes: figure 22. int assertion scheme with t int_idle /cs /int 1 st event occurance register read (int_stat register) t t int_idle /int pin is not asserted until t int_idle has expired register read (int_stat register) 2 nd event occurance /cs /int event occurance register read (int_stat register) t int_active t t int_inactive t x int_stat register content cleared x /int pin will not be re- asserted t int_inactive after /int returns high
25 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.9.3 microcontroller wake-up when used together with external pnp transistors the int pin could also be used for wake-up purpose to activate a voltage regulator via its inhibit inputs (see figure 23 ). this is especially useful for waking up a microcontroller in sleep mode to allow significant system-level power savings. before the wake-up, the v dd could be unavailable to the TIC12400-Q1 and the int pin can be pulled up externally to the v s voltage. when an event (switch status change, temperature warning, or ov ? etc) takes place, the int pin will be asserted low to activate the voltage regulator, which in turn activates the microcontroller to enable the communication between the microcontroller and the TIC12400-Q1. the event information is stored inside the device interrupt register (int_stat) for the microcontroller's retrieval when the communication is reestablished. the wake-up implementation is applicable only when the device is configured to use the static int assertion scheme. figure 23. int connection to support microcontroller wake-up 8.3.9.4 interrupt enable / disable and interrupt generation conditions each switch input can be programmed to enable or disable interrupt generation upon status change by configuring registers int_en_comp1 to int_en_comp2 (for comparator inputs) and int_en_cfg1 to int_en_cfg4 (for adc inputs). interrupt generation condition can be adjusted for thres_com (for in0-in11) by adjusting the in_com_en bit in the matrix register. the abovementioned registers can also be used to control interrupt generation condition based on the following settings: 1. rising edge : an interrupt is generated if the current input measurement is above the corresponding threshold and the previous measurement was below. 2. falling edge: an interrupt is generated if the current input measurement is below the corresponding threshold and the previous measurement was above. 3. both edges : changes of the input voltage in either direction results in an interrupt generation. note interrupt generation from switch status change is disabled for all inputs by default upon device reset. TIC12400-Q1 agnd 10k gnd microcontroller v dd /int agnd gnd gpi v dd + gnd en regulator v in v out inh v bat
26 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.9.5 detection filter when monitoring the switch input status a detection filter can be configured by setting the det_filter bits in the config register to generate switch status change (ssc) interrupt only if the same input status (w.r.t the threshold) is sampled consecutively. this detection filter can be useful to debounce inputs during a switch toggle events. four different filtering schemes are available: 1. generate an ssc interrupt if the voltage level at an input crossed its threshold 2. generate an ssc interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t. the threshold) for at least 2 consecutive polling cycles 3. generate an ssc interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t. the threshold) for at least 3 consecutive polling cycles 4. generate an ssc interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t. the threshold) for at least 4 consecutive polling cycles the default value of switch status is stored internally after the 1st detection cycle, even if detection filter (by configure the det_filter in the config register) is used. an example is illustrated below with the assumption that det_filter in register config is set to 11 (ssc interrupt is generated if the input crosses the threshold and the status is stable w.r.t. the threshold for at least 4 consecutive detection cycles). assume switch status change is detected in the 3rd detection cycle and stays the same for the next 3 cycles. detection cycle 1 2 3 4 5 6 event ? default switch status stored ? int asserted ? ssc flagged ? switch status change detected ? ? ? int asserted ? ssc flagged the detection filter applies to all enabled inputs regardless of their input modes (adc or comparator) selection. the detection filter counter is reset to 0 when the trigger bit in the config register is de-asserted to logic 0. upon device reset, the default setting for the detection filter is set to generating an ssc interrupt at every threshold crossing. note the detection filter does not apply to the common threshold thres_com. 8.3.10 temperature monitor with multiple switch inputs are closed and high wetting current setting is enabled, considerable power could be dissipated by the device and raise the device temperature. TIC12400-Q1 has integrated temperature monitoring and protection circuitry to put the device in low power mode to prevent damage due to overheating. two types of temperature protection mechanisms are integrated in the device: temperature warning (tw) and temperature shutdown (tsd). the triggering temperatures and hysteresis are specified in table 4 below: table 4. temperature monitoring characteristics of TIC12400-Q1 parameter min typ max unit temperature warning trigger temperature (t tw ) 130 140 155 c temperature shutdown trigger temperature (t tsd ) 150 160 175 c temperature hysteresis (t hys ) for t tw and t tsd 15 c 8.3.10.1 temperature warning (tw) when the device temperature goes above the temperature warning trigger temperature (t tw ), the TIC12400-Q1 performs the following operations: 1. generate an interrupt by asserting the int pin low and flag the tw bit in int_stat register to logic 1. the temp bit in the spi flag is also flagged to logic 1 for all spi transactions. 2. the tw_stat bit of the in_stat_misc register is flagged to logic 1. 3. if the tw_cur_dis_cso or tw_cur_dis_cso bit in config register is set to logic 0 (default), the wetting current is adjusted down to 2 ma for 10 ma or 15 ma settings. the wetting current stays at its pre- configured value if 0 ma, 1 ma, 2 ma, or 5 ma setting is used. 4. maintain the low wetting current as long as the device junction temperature stays above t tw - t hys .
27 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the int pin is released and the int_stat register content is cleared on the rising edge of cs provided the int_stat register has been read during cs low. the TIC12400-Q1 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above t tw - t hys . the status bit tw_stat in register in_stat_misc continues to stay at logic 1 as long as the temperature warning condition exists. if desired, the reduction of wetting current down to 2ma setting (from 10 ma or 15 ma) can be disabled by setting the tw_cur_dis_cso or tw_cur_dis_csi bit in the config register to 1. the interrupt is still generated ( int asserted low and int_stat interrupt register is updated) when the temperature warning event occurs but the wetting current is not reduced. this setting applies to both the polling and continuous mode operation. note if the feature is enabled, switch detection result might be impacted upon t tw event if the wetting current is reduced to 2ma from 10ma or 15ma. when the temperature drops below t tw - t hys , the int pin is asserted low (if released previously) to notify the microcontroller that the temperature warning condition no longer exists. the tw bit of the interrupt register int_stat is flagged logic 1. the tw_stat bit in the in_stat_misc register is de-asserted back to logic 0. the device resumes operation using the current programmed settings (regardless of the int and cs status). 8.3.10.2 temperature shutdown (tsd) after the device enters tw condition, if the junction temperature continues to rise and goes above the temperature shutdown threshold (t tsd ), the TIC12400-Q1 enters the temperature shutdown (tsd) condition and performs the following operations: 1. opens all the switches connected to the current sources/sinks to prevent any further heating due to excessive current flow. 2. generate an interrupt by asserting the int pin (if not already asserted) low and flag the tsd bit in the int_stat register to logic 1. the temp bit in the spi flag is also flagged to logic 1 for all spi transactions. 3. the tsd_stat bit of the in_stat_misc register is flagged to logic 1. the tw_stat bit also stays at logic 1. 4. spi communication stays on and all register settings stay intact without resetting. previous switch status, if needed, can be retrieved without any interruption. 5. maintain the setting as long as the junction temperature stays above t tsd - t hys . the int pin is released and the int_stat register content is cleared on the rising edge of cs provided the int_stat register has been read during cs low. the TIC12400-Q1 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above t tsd - t hys . the status bit tsd_stat in register in_stat_misc continues to stay at logic 1 as long as the temperature shutdown condition exists. when the temperature drops below t tsd - t hys , the int pin is asserted low (if released previously) to notify the microcontroller that the temperature shutdown condition no longer exists. the tsd bit of the interrupt register int_stat is flagged logic 1. in the in_stat_misc register, the tsd_stat bit is de-asserted back to logic 0, while the tw_stat bit stays at logic 1. the device resumes operation using the wetting current setting described in section temperature warning if the temperature stays above t tw - t hys . note the polling restarts from the first enabled channel and the ssc interrupt is generated at the end of the first polling cycle. the detected switch status from the first polling cycle becomes the default switch status for subsequent polling. 8.3.11 parity check and parity generation the TIC12400-Q1 uses parity bit check to ensure error-free data transmission from/to the spi master. the device uses odd parity, for which the parity bit is set so that the total number of ones in the transmitted data on so (including the parity bit) is an odd number (i.e. bit0 bit1 ? bit30 bit31 parity = 1). the device also uses odd parity check after receiving data on si from the spi master. if the total number of ones in the received data (including the parity bit) is an even number the received data is discarded. the int will be asserted low and the prty_fail bit in the interrupt register (int_stat) is flagged to logic 1 to notify the host that transmission error occurred. the prty_fail flag is also asserted during spi communications.
28 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.12 cyclic redundancy check (crc) the TIC12400-Q1 includes a crc module to support redundancy checks on the configuration registers to ensure the integrity of data. the crc calculation is based on the itu-t x.25 implementation, and the crc polynomial (0x1021) used is popularly known as crc-ccitt-16 since it was initially proposed by the itu-t (formerly ccitt) committee. the crc calculation rule is defined in table 5 : table 5. crc calculation rule crc rule value crc result width 16 bits polynomial x 16 + x 12 + x 5 +1 (1021h) initial (seed) value ffffh input data reflected no result data reflected no xor value 0000h the crc calculation is done on all the configuration registers starting from register config and ending at register mode . the device substitutes a ? zero ? for each reserved configuration register bit during the crc calculation. the crc calculation can be triggered by asserting the crc_t bit in the config register. once completed, the crc_calc interrupt bit in the int_stat register is asserted and an interrupt is issued. the 16- bit crc calculation result is stored in the register crc. this interrupt can be disabled by de-asserting the crc_calc_en bit in the int_en_cfg0 register. it is important to avoid writing data to the configuration registers when the device is undergoing crc calculations to prevent false calculation results. figure 24 shows the block diagram of the crc module. the module consists of 16 shift-registers and 3 exclusive-or gates. the registers start with 1111-1111-1111-1111 (or ffffh) and the module performs an xor function and shifts its content until the last bit of the register string is used. the final register ? s content after the last data bit is the calculated crc value of the data set and the content is stored in the crc register. note the crc_t bit self-clears after the crc calculation is completed. logic 1 is used for crc_t bit during crc calculation. figure 24. ccitt-16 crc module block diagram msb x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 data xor xor lsb + + + xor
29 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4 device functional modes the TIC12400-Q1 has 2 modes of operation: continuous mode and polling mode. the following sections describe the two operation modes in details as well as some of the advanced features that could be activated during normal operations. 8.4.1 continuous mode in continuous mode, wetting current is continuously applied to each enabled input channel, and the status of each channel is sampled sequentially (starting from the in0 to in23). the TIC12400-Q1 monitors enabled inputs and issues an interrupt (if enabled) if a switch status change event is detected. the wetting current setting for each input can be individually adjusted by configuring the wc_cfg0 and wc_cfg1 to the 0ma, 1ma, 2ma, 5ma, 10ma, or 15ma setting. each input is monitored by either a comparator or an adc depending on the setting of the input mode in the register mode . figure 25 below illustrates an example of the timing diagram of the detection sequence in continuous mode. after the trigger bit in register config is set to logic 1, it takes t startup to activate the wetting current for all enabled inputs. the wetting currents stay on continuously, while each input is routed to the adc/comparator for sampling in a sequential fashion. after conversion/comparison is done for an input, the switch status (below or above detection threshold) is stored in registers ( in_stat_comp for comparator inputs and in_stat_adc0 to in_stat_adc1 for adc inputs) to be used as the default state for subsequent detection cycles. the digital values (if the input is configured as adc input mode) are stored in the registers ana_stat0 to ana_stat11 . after the end of the first polling cycle, the int pin is asserted low to notify the microcontroller that the default switch status is ready to be read. the ssc bit in int_stat register and the spi status flag ssc are also asserted to logic 1. the polling cycle time (t poll ) determines how frequently each input is sampled and can be configured in the register config . figure 25. an example of the detection sequence in continuous mode trigger bit set to logic 1 in config register t t startup t wetting current time in0 in1 in3 in23 /int x default input status is stored x /int pin is asserted after the 1 st detection cycle ... t t poll_time t input sampling restarts from first enabled input after t poll_time t t adc or t comp t t t adc or t comp t
30 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) the int_stat register is cleared and int pin de-asserted if a spi read command is issued to the register. note the interrupt is always generated after the 1st detection cycle (after the trigger bit in register config is set to logic 1). in subsequent detection cycles, the interrupt is generated only if switch status change is detected. no wetting currents are applied to 0ma- configured inputs, although some biasing current (as specified by i in_leak_0ma ) may still flow in and out of the input. threshold crossing monitoring is still performed for the input using the defined threshold(s). the 0ma setting is useful to utilize the integrated adc or comparator to measure applied voltage on a specific input without being affected by the device wetting current. 8.4.2 polling mode the polling mode can be activated to reduce current drawn in ignition-off condition to conserve battery charge. unlike the continuous mode, the current sources/sinks do not stay on continuously in the polling mode. instead, they are turned on/off sequentially from in0 to in23 and cycled through each individual input channel. the microcontroller can be put to sleep to reduce overall system power. if a switch status change (ssc) is detected by the TIC12400-Q1, the int pin (if enabled for the input channel) is asserted low (and the ssc bit in int_stat register and the spi status flag ssc are also asserted to logic 1). the int pin assertion can be used to wake up the system regulator which, in turn, wakes up the microcontroller as described in section microcontroller wake- up . the microcontroller can then use spi communication to read the switch status information. the polling is activated when the trigger bit in the config register is set to logic 1. there are 2 different polling schemes that can be configured in TIC12400-Q1: standard polling and matrix polling. 8.4.2.1 standard polling in standard polling mode, wetting current is applied to each input for a pre-programmed polling active time between 64 s and 2048 s, set by the poll_act_time bits in the config register . at the end of the wetting current application, the input voltage is sampled by the comparator (if input is configured as comparator input mode) or the adc (if input is configured as adc input mode). each input is cycled through in sequential order from in0 to in23. sampling is repeated at a frequency from 2 ms to 4096 ms, set by the poll_time bits in the config register . wetting currents are applied to closed switches only during the polling active time; hence the overall system current consumption can be greatly reduced. similar to continuous mode, after the first polling cycle, the switch status of each input (below or above detection threshold) is stored in registers ( in_stat_comp for comparator inputs and in_stat_adc0 to in_stat_adc1 for adc inputs) to be used as the default state for subsequent polling cycles. the digital values (if the input is configured as adc input mode) are stored in the registers ana_stat0 to ana_stat11 . the int pin is asserted low to notify the microcontroller that the default switch status is ready to be read. the ssc bit in int_stat register and the spi status flag ssc are also asserted to logic 1. the int_stat register is cleared and int pin de-asserted if a spi read command is issued to the register. note the interrupt is always generated after the 1st polling cycle (after the trigger bit in register config is set to logic 1). in subsequent polling cycles the interrupt is generated only if switch status change is detected. an example of the timing diagram of the polling mode operation is shown in figure 26 .
31 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) figure 26. an example of the polling sequence in standard polling mode trigger bit set to logic 1 in config register t t startup t wetting current time in0 in1 in3 in23 /int x default input status is stored x /int pin is asserted after the 1 st detection cycle ... t t poll_time t ... t t startup t t t poll_act_time t t t poll_act_time t input sampling restarts from first enabled input after t poll_time wetting current is activated for t poll_act_time t t adc or t comp t t t adc or t comp t t t adc or t comp t
32 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) if the switch position changes between two active polling times, no interrupt will be generated and the status registers ( in_stat_comp for comparator inputs and in_stat_adc0 to in_stat_adc1 for adc inputs) will not reflect such a change. an example is shown in figure 27 . figure 27. example for ignored switch position change between 2 wetting current cycles time wetting current /int initial switch state change switch state /cs ignored switch state change /int asserted due to initial state change
33 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) 8.4.2.2 matrix polling figure 28. TIC12400-Q1 matrix configuration 1ma to 15ma or off v s esd protection 27 33 29 30 31 in9 in10 sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw sw 32 in8 in7 in6 in5 in4 1ma to 15ma or off esd protection agnd 1ma to 15ma or off v s esd protection 1ma to 15ma or off esd protection agnd in11 in12 in13 in14 in15 6 x 6 matrix 5 x 5 matrix 4 x 4 matrix 3 2 1 36 35 34 ... ... copyright ? 2016, texas instruments incorporated TIC12400-Q1
34 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) from in4 to in15 a special input switch matrix (see figure 28 ) can be configured and monitored in addition to the standard switches to gnd and v bat . this feature could be useful to monitor a special switch input configuration called matrix inputs as required by some specific oems. three different matrix configurations are possible, and are defined by matrix bits in the matrix register. if the matrix bits are set to ? 00 ? all inputs are treated as standard inputs with identical polling active time according to the poll_act_time bits in the config register. any settings other than ? 00 ? for matrix bits causes the polling active time for the matrix inputs to be configured according to poll_act_time_m bits in the matrix register. inputs that are not part of the matrix configuration will be configured using the poll_act_time bits in the config register. t poll_act_time_m should be configured properly to allow sufficient time for the current source/sink to charge/discharge the capacitors (if any) connected to the switch inputs. table 6. TIC12400-Q1 matrix configuration settings input 4 x 4 matrix 5 x 5 matrix 6 x 6 matrix current source or sink polling active time setting current source or sink polling active time setting current source or sink polling active time setting in4 csi poll_act_time_ m csi poll_act_time_m csi poll_act_time_m in5 csi csi csi in6 csi csi csi in7 csi csi csi in8 configurable to cso or csi poll_act_time csi csi in9 configurable to cso or csi configurable to cso or csi poll_act_time csi in10 cso poll_act_time_ m cso poll_act_time_m cso in11 cso cso cso in12 cso cso cso in13 cso cso cso in14 cso poll_act_time cso cso in15 cso cso poll_act_time cso the TIC12400-Q1 implements a different polling scheme when matrix input is configured. after the polling sequence is started (by setting trigger bit in config register to logic 1), the polling takes place within the matrix input group first before the rest of the standard inputs are polled. after the matrix inputs are polled, the switch status of each input combination (below or above detection threshold) is stored internally in registers in_stat_matrix0 and in_stat_matrix1 , and it is used as the default state for subsequent matrix polling cycles. the standard inputs follow the same polling behavior as described in section standard polling . after the polling cycle is completed on matrix and standard inputs, the int pin is asserted low to notify the microcontroller that the default switch status is ready to be read. the ssc bit in the int_stat register and the spi status flag ssc are also asserted to logic 1. the int_stat register is cleared and int pin de-asserted if a spi read command is issued to the register. note the interrupt is always generated after the 1st complete polling cycle (after the trigger bit in register config is set to logic 1). in subsequent polling cycles, the interrupt is generated only if switch status change is detected.
35 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated note the following programming requirement when using the matrix polling: ? it is critical to program the cso/csi configuration for each matrix input appropriately according to table 6 to avoid incorrect switch status detection. ? it is mandatory to set higher wetting current for the sinks (in4-in9) than the sources (in10-in15). the actual current flowing through the external switches will be the lesser of the two settings. if the same setting is used for both the sink and the source, the detected result might be incorrect. because of this, the 15 ma setting shall not be used for the current sources and the 1 ma setting shall not be used for the current sinks. depending on the type of matrix switches, the TIC12400-Q1 might require some specific wetting current settings to be able to distinguish between switch open/closed states. ? if tw_cur_dis_cso or tw_cur_dis_csi is set to logic 0 in the config register, wetting current is reduced to 2 ma for 10 ma and 15 ma settings upon tw event. since it ? s mandatory to have higher wetting current for the sinks (in4-in9) than the sources (in10-in15) during matrix polling, table 7 below summarizes the only possible settings if tw event is expected: table 7. possible wetting current settings for the matrix polling mode if tw_cur_dis=0 and tw event is expected cso (in10-in15) csi (in4-in9) resulting wetting current 1 ma 2 ma, 5 ma, 10 ma, 15 ma 1 ma 2 ma 5 ma 2 ma if higher wetting current is needed and tw event might be expected, the tw wetting current reduction feature needs to be disabled by setting tw_cur_dis_cso or tw_cur_dis_csi bit in the config register to 1. ? only comparator input mode is supported for the matrix polling. do not program the matrix inputs into adc input mode. the comparison takes place on the source side (in10-in15) since the sink side is pulled to ground. interrupt generation condition can be set by configuring the int_en_comp1 and int_en_comp2 registers for inputs in10 to in15. some programmability is removed when matrix polling mode is used, as listed below: ? to keep the polling scheme simple, the ability to disable inputs is removed for the matrix inputs. only 3 configurations (4x4, 5x5, and 6x6) can be used for the matrix polling. standard inputs outside the matrix input group can still be disabled, if desired. ? detection filter (by configuring the det_filter in the config register) does not apply to the matrix inputs, but still applies to the standard inputs outside the matrix input group. ? when matrix polling is selected, continuous mode is not available to the standard inputs outside the matrix input group.
36 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 29 illustrates an example of the polling sequence for the 6x6 matrix input configuration: figure 29. polling scheme for 6x6 matrix inputs t t poll_act_time t time wetting current /int /cs x default input status is stored x /int pin is asserted after the 1 st detection cycle in10 trigger bit set to logic 1 in config register t t poll_time t t startup t poll_act_time_m t startup t t adc or t comp t in11 in12 in13 in14 in15 in0 in1 in2 in3 in16 in17 ... ... in23 read on int_stat register release the /int pin in4 to gnd in5 to gnd in6 to gnd in7 to gnd in8 to gnd in9 to gnd
37 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 30 illustrates an example of the polling sequence for the 5x5 matrix input configuration. note the input in9 and in15 are included in the standard polling sequence. figure 30. polling scheme for 5x5 matrix inputs t startup t t poll_act_time t time wetting current /int /cs x default input status is stored x /int pin is asserted after the 1 st detection cycle in10 trigger bit set to logic 1 in config register t t poll_time t t poll_act_time_m t startup t t adc or t comp t in11 in12 in13 in14 in0 in1 in2 in3 in9 in15 ... ... in23 read on int_stat register release the /int pin in4 to gnd in5 to gnd in6 to gnd in7 to gnd in8 to gnd
38 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 31 illustrates an example of the polling sequence for the 4x4 matrix input configuration. note inputs in8, in9, in14, and in15 are included in the standard polling sequence. figure 31. polling scheme for 4x4 matrix inputs t startup t t poll_act_time t time wetting current /int /cs x default input status is stored x /int pin is asserted after the 1 st detection cycle in10 trigger bit set to logic 1 in config register t t poll_time t t poll_act_time_m t startup t t adc or t comp t in11 in12 in13 in0 in1 in2 in3 in8 in9 ... ... in23 read on int_stat register release the /int pin in4 to gnd in5 to gnd in6 to gnd in7 to gnd in14
39 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.3 additional features there are additional features that can be enabled during continuous and polling mode to increase robustness of device operation or provide more system information. these features are described in detail in the following sections. 8.4.3.1 clean current polling (ccp) to detect resistor coded switches or reduce overall power consumption of the chip, a lower wetting current setting is recommended. however, certain system design requires 10 ma or higher cleaning current to clear oxide build-up on the mechanical switch contact surface when the current is applied to closed switches. a special type of polling, called the clean current polling (ccp), can be used for this application. if ccp is enabled each polling cycle consists of two wetting current activation steps. the first step uses the wetting current setting configured in the wc_cfg0 and wc_cfg1 registers as in the continuous mode or polling mode. the second step (cleaning cycle) is activated simultaneously for all ccp enabled inputs at a time t ccp_tran after the normal polling step of the last enabled input. interrupt generation and int pin assertion is not impacted by the clean current pulses. the wetting current and its active time for the cleaning cycle can be configured in the ccp_cfg0 register. the cleaning cycle can be disabled, if desired, for each individual input by programming the ccp_cfg1 register. ccp is available for both continuous mode and polling mode. to use the ccp feature, at least one input (standard or matrix) or the v s measurement has to be enabled. note that although ccp can be enabled in matrix polling mode, it is not an effective way to clean the matrix switch contact, since the current supplied from the TIC12400-Q1 is divided and distributed across multiple matrix channels.
40 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 32 illustrates the operation of the ccp when the device is configured to the standard polling mode. figure 32. standard polling with ccp enabled time wetting current /int /cs x default input status is stored x /int pin is asserted after the 1 st detection cycle trigger bit set to logic 1 in config register t t poll_time t t t adc or t comp t in0 in1 in2 ... in23 read on int_stat register release the /int pin in22 ... t t ccp_tran t t t ccp_time t t startup t startup
41 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 33 illustrates the operation of the ccp when the device is configured to the continuous mode: figure 33. continue mode with ccp enabled 8.4.3.2 wetting current auto-scaling the 10 ma and 15 ma wetting current settings are useful to clean oxide build-up on the mechanical switch contact surface when the switch changes state from open to close. after the switch is closed, it is undesirable to keep the wetting current level at high level if only digital switches are monitored since it results in high current consumption and could potentially heat up the device quickly if multiple inputs are monitored. the wetting current auto-scaling feature helps mitigate this issue. when enabled (auto_scale_dis_cso or auto_scale_dis_csi bit = logic 0 in the wc_cfg1 register), wetting current is reduced to 2 ma from 10 ma or 15 ma setting after switch closure is detected. the threshold used to determine a switch closure is the threshold configured in the thres_comp register for inputs configured as comparator input mode. for inputs configured as adc input mode, the threshold used to determine a switch closure depends on the input number, as described in table 8 below. table 8. threshold used to determine a switch closure for wetting current auto-scaling for adc inputs input threshold used to determine a switch closure in0-in11 mapped threshold from thres0 to thres7 in12 to in17 thres2b in18 to in22 thres3c in23 thres9 time wetting current /int /cs x default input status is stored x /int pin is asserted after the 1 st detection cycle trigger bit set to logic 1 in config register t t poll_time t t t adc or t comp t in0 in1 in2 ... in23 read on int_stat register release the /int pin in22 ... t t ccp_time t t startup t startup
42 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the current reduction takes place n cycles after switch closure is detected on an input, where n depends on the setting of the det_filter bits in the config register: ? det_filter= 00: wetting current is reduced immediately in the next detection cycle after a closed switch is detected. ? det_filter= 01: wetting current is reduced when a closed switch is detected and the switch status is stable for at least 2 consecutive detection cycles. ? det_filter= 10: wetting current is reduced when a closed switch is detected and the switch status is stable for at least 3 consecutive detection cycles. ? det_filter= 11: wetting current is reduced when a closed switch is detected and the switch status is stable for at least 4 consecutive detection cycles. the wetting current is adjusted back to the original setting of 10 ma or 15 ma at a time of n cycles after an open switch is detected, where n again depends on the det_filter bit setting in the config register. figure 34 depicts the behavior of the wetting current auto-scaling feature. figure 34. wetting current auto-scaling behavior the wetting current auto-scaling only applies to 10 ma and 15 ma settings and is only available in continuous mode. if auto_scale_dis_cso or auto_scale_dis_csi bit is set to logic 1 in the wc_cfg1 registers, the wetting current stays at its original setting when a closed switch is detected. power dissipation needs to be closely monitored when wetting current auto-scaling is disabled for multiple inputs as the device could heat up quickly when high wetting current settings are used. if the auto-scaling feature is disabled in continuous mode, the total power dissipation can be approximated using equation 1 . (1) where i wett (total) is the sum of all wetting currents from all input channels. increase in device junction temperature can be calculated based on p r ja . the junction temperature must be below t tsd for proper device operation. an interrupt will be issued when the junction temperature exceeds t tw or t tsd . for detailed description of the temperature monitoring, please refer to sections temperature warning (tw) and temperature shutdown (tsd) . 8.4.3.3 v s measurement when the TIC12400-Q1 is used to monitor resistor-coded switches, the v s supply voltage level becomes critical. if v s is not sufficiently high, the device might not have enough headroom to produce accurate wetting currents. this could impact the accuracy of the switch status monitoring. it is imperative for the microcontroller to have knowledge of the v s voltage on a constant basis in such a case. measurement of v s voltage is a feature in TIC12400-Q1 that can be enabled by setting the vs_meas_en bit in register config to logic 1. if enabled, at the end of every detection/polling cycle, the voltage on the v s pin is sampled and converted by the adc to a digital value. the conversion takes one extra t adc , and the converted value is recorded in the ana_stat12 register. the v s measurement supports two different v s voltage ranges that can be configured by the vs_ratio bit in the config register. by default (vs_ratio= logic 0), the supported v s voltage range is from 4.5 v to 9 v, and v s voltage in excess of 9 v results in a saturated adc raw code of 1023. this setting provides better measurement resolution at lower v s voltages. when vs_ratio bit is set to logic 1, the supported v s voltage range is widened to 4.5 v to 30 v, and v s voltage in excess of 30 v results in a saturated adc raw code of 1023. this setting allows wider measurement range but more coarse measurement resolution. it is important to adjust the detection thresholds accordingly depending on the v s voltage range configured. ) ( _ total wett cont s s total i i v p u auto-scaling disabled auto-scaling enabled 0ma 0ma switch open switch closed 15ma 15ma 2ma
43 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated four different measurement thresholds can be programmed by the TIC12400-Q1: vs0_thres2a/b and vs1_thres2a/b. the value of these thresholds can be programmed by configuring registers thres_cfg0 to thres_cfg3 and the mapping can be programmed by configuring registers thresmap_vs0_thres2a/b and thresmap_vs1_thres2a/b bits in the register thresmap_cfg2 . when setting the thresholds follow the rules in table 9 below. table 9. proper threshold configuration for v s measurements v s threshold proper threshold configuration vs0 vs0_thres2b vs0_thres2a vs1 vs1_thres2b vs1_thres2a after the v s measurement is enabled for the first time, the v s measurement interrupt is always generated ( int pin is asserted low, and the vs0 or vs1 bit in the int_stat register is flagged to logic 1) at the end of the first polling cycle to notify the microcontroller the initial v s measurement result is ready to be retrieved. the vs0_stat and vs1_stat bits from register in_stat_misc indicate the status of the v s voltage with respect to the thresholds, and the ana_stat12 register stores the converted digital value of the v s voltage. the spi status flag vs_th is also asserted to logic 1 during spi communications. note the status detected in the first polling cycle becomes the baseline value of comparison for subsequent v s measurements and the interrupt will be generated only if threshold crossing is detected. similar to regular inputs, the interrupt generation conditions can be programmed by setting the vs_th0_en and vs_th1_en bits in the int_en_cfg4 register to the following settings: 1. rising edge : an interrupt is generated if the current v s measurement is above the corresponding threshold and the previous measurement was below. 2. falling edge : an interrupt is generated if the current v s measurement is below the corresponding threshold and the previous measurement was above. 3. both edges : changes of the v s measurement status in either direction results in an interrupt generation. interrupt generation can also be disabled by setting vs_th0_en or vs_th1_en to logic 0 in register int_en_cfg4 . once disabled, v s voltage crossing does not flag the vs0 or vs1 bit in int_stat register and does not assert int pin low. to only mask the int pin from assertion (while keeping int_stat register updated), configure the vs1_en and vs0_en bits in register int_en_cfg0 to logic 0. note the v s measurement is only intended to be used as part of switch detection sequence to determine the validity of the switch detection states that are reported by the TIC12400-Q1. it is not intended to be used for standalone supply monitoring, such as monitoring cranking voltages, due to the potentially delayed response being part of the polling sequence. the v s measurement result is accurate for v s above 4.5 v. by default, the v s voltage measurement is disabled upon device reset. 8.4.3.4 wetting current diagnostic when the TIC12400-Q1 is used to monitor safety-critical switches, it might be valuable for the microcontroller to have knowledge of the operating status of the wetting current sources/ sinks. this can be achieved by activating the wetting current diagnostic feature provided for inputs in0 to in3. in0 and in1 can be diagnosed for defective wetting current sources, while in2 and in3 can be diagnosed for defective current sinks. the wetting current diagnostic feature can be activated by setting the wet_d_inx_en bits in the config register to 1 for the desired inputs, where x can be 0, 1, 2, or 3. if activated, the TIC12400-Q1 checks the status of the wetting current sources / sinks for the configured input periodically as part of the polling sequence. if the wetting current is determined to be flawed, the TIC12400-Q1 pulls the int pin low to notify the host and flag the wet_diag bit in the int_stat register to logic 1. the oi bit in the spi flag is also asserted during spi transactions. the microcontroller can then read bits in0_d to in3_d in register in_stat_misc to learn more information on which wetting current source/sink is defective. the wetting current diagnostic is not performed for inputs that are disabled (in_en_x bit = 0 in the in_en register) from polling, even if the feature is activated for those inputs. also, it is critical to configure the current source/sink appropriately (cso for in0/in1 and csi for in2/in3) and program the input to adc input mode before activating the wetting current diagnostic feature to prevent false interrupts from being generated. the wetting current diagnostic feature can be performed regardless of the states of external switches, and it is available in both continuous mode and polling mode.
44 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 35 shows an example of the feature carried out in a typical polling sequence. in this example, it can be observed that the wetting current is activated for duration of t poll_act + t adc for each input diagnosed (in0 or in2). normal polling sequence resumes with in4 and the wetting current is activated for t poll_act for the rest of the inputs. the diagnostic is not executed on inputs in1 and in3 in this example since they are disabled. figure 35. an example of the polling sequence in standard polling mode with wetting current diagnostic enabled 8.4.3.5 adc self-diagnostic in addition to the wetting current diagnostic, another feature ? the adc self-diagnostic, can be enabled to monitor the integrity of the internal adc. the adc self-diagnostic feature is activated by setting the adc_diag_t bit in the config register to logic 1. once enabled, the TIC12400-Q1 periodically sends a test voltage to the adc. the conversion result is stored in the adc_self_ana bits in the register ana_stat12 and is compared with a pre-defined code to determine whether the conversion is performed properly. if an error is detected, the TIC12400-Q1 pulls the int pin low to notify the host and flag the adc_diag bit in the int_stat to logic 1. the bit adc_d in register in_stat_misc is updated with the result from the self-diagnostic. the adc self-diagnostic feature is available in both continuous mode and polling mode. trigger bit set to logic 1 in config register t t startup t wetting current time in0 in2 in4 in23 /int x default input status is stored x /int pin is asserted after the 1 st detection cycle ... t t poll_time t ... t t startup t t t poll_act_time t input sampling restarts from first enabled input after t poll_time wetting current is activated for t poll_act_time + t adc (or t comp ) for channels with wcd enabled t t adc or t comp t t t adc or t comp t t t adc or t comp t t t adc or t comp t
45 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5 programming the spi interface communication consists of the 4 pins: cs, sclk, si, and so. the interface can work with sclk frequency up to 4mhz. 8.5.1 spi communication interface buses 8.5.1.1 chip select ( cs) the system microcontroller selects the TIC12400-Q1 to receive communication using the cs pin. with the cs pin in a logic low state, command words may be sent to the TIC12400-Q1 via the serial input (si) pin, and the device information can be retrieved by the microcontroller via the serial output (so) pin. the falling edge of the cs enables the so output and latches the content of the interrupt register int_stat. the microcontroller may issue a read command to retrieve information stored in the registers. rising edge on the cs pin initiates the following operations: 1. disable the output driver and makes so high-impedance. 2. int pin is reset to logic high if a read command to the int_stat register was issued during cs = low. to avoid corrupted data, it is essential the high-to-low and low-to-high transitions of the cs signal occur only when sclk is in a logic low state. a clean cs signal is needed to ensure no incomplete spi words are sent to the device. the cs pin should be externally pulled up to vdd by a 10 k resistor. 8.5.1.2 system clock (sclk) the system clock (sclk) input is used to clock the internal shift register of the TIC12400-Q1. the si data is latched into the input shift register on the falling edge of the sclk signal. the so pin shifts the device stored information out on the rising edge of sclk. the so data is available for the microcontroller to read on the falling edge of sclk. false clocking of the shift register must be avoided to ensure validity of data and it is essential the sclk pin be in a logic low state whenever cs makes any transition. therefore, it is recommended that the sclk pin gets pulled to a logic low state as long as the device is not accessed and cs is in a logic high state. when the cs is in a logic high state, any signal on the sclk and si pins will be ignored and the so pin remains as a high impedance output. refer to figure 36 and figure 37 for examples of typical spi read and write sequence. 8.5.1.3 slave in (si) the si pin is used for serial instruction data input. si information is latched into the input register on the falling edge of the sclk. to program a complete word, 32 bits of information must be entered into the device. the spi logic counts the number of bits clocked into the ic and enables data latching only if exactly 32 bits have been clocked in. in case the word length exceeds or does not meet the required length, the spi_fail bit of the int_stat register is asserted to logic 1 and the int pin will be asserted low. the data received is considered invalid. note the spi_fail bit is not flagged if sclk is not present. 8.5.1.4 slave out (so) the so pin is the output from the internal shift register. the so pin remains high-impedance until the cs pin transitions to a logic low state. the negative transition of cs enables the so output driver and drives the so output to the high state (by default). the first positive transition of sclk makes the status data bit 31 available on the so pin. each successive positive clock makes the next status data bit available for the microcontroller to read on the falling edge of sclk. the si/so shifting of the data follows a first-in, first-out scheme, with both input and output words transferring the most significant bit (msb) first.
46 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) 8.5.2 spi sequence figure 36 and figure 37 depict the spi communication sequence during read and write operations for the TIC12400-Q1. figure 36. TIC12400-Q1 read spi sequence figure 37. TIC12400-Q1 write spi sequence 8.5.2.1 read operation the read/write bit (bit 31) of the si bus needs to be set to logic 0 for a read operation. the 6-bits address of the register to be accessed follows next on the si bus. the content from bit 24 to bit 1 does not represent a valid command for a read operation and will be ignored. the lsb (bit 0) is the parity bit used to detect communication errors. on the so bus, the status flags will be outputted from the TIC12400-Q1, followed by the data content in the register that was requested. the lsb is the parity bit used to detect communication errors. note there are several test mode registers used in the TIC12400-Q1 in addition to the normal functional registers, and a read command to these test registers returns the register content. if a read command is issued to an invalid register address, the TIC12400-Q1 returns all 0 ? s. 8.5.2.2 write operation the read/write bit (bit 31) on the si bus needs to be set to 1 for a write operation. the 6-bits address of the register to be accessed follows next on the si bus. note the register needs to be a writable configuration register, or otherwise the command will be ignored. the content from bit 24 to bit 1 represents the data to be written to the register. the lsb (bit 0) is the parity bit used to detect communication errors. si bit 31 (msb) bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 1 bit 0 (lsb) read/ write 1 register address data in par ... so bit 31 (msb) bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 1 bit 0 (lsb) status flag por previous content of the register addressed par ... spi_ fail prty_ fail ssc vs_th temp oi si bit 31 (msb) bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 1 bit 0 (lsb) read/ write 0 register address 'rq?wfduh par ... so bit 31 (msb) bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 1 bit 0 (lsb) status flag por data out par ... spi_ fail prty_ fail ssc vs_th temp oi
47 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated programming (continued) on the so bus, the status flags will be output from the TIC12400-Q1, followed by the previous data content of the written register. the previous content of the register is latched after the full register address is decoded in the si command (after bit 25 is transmitted). the new data will replace the previous data content at the end of the spi transaction if the si write is a valid command (valid register address and no spi/parity error). if the write command is invalid, the new data will be ignored and the register content will remain unchanged. the lsb is the parity bit used to detect communication errors. note there are several test mode registers used in the TIC12400-Q1 in addition to the normal functional registers. a write command to these test registers has no effect on the register content, even though the register content is returned on the so output. if a write command is issued to an invalid register address, the so output returns all 0 ? s. 8.5.2.3 status flag the status flags are output from so during every read or write spi transaction to indicate system conditions. these bits do not belong to an actual register, but their content is mirrored from the interrupt register int_stat. a read command executed on the int_stat would clear both the bits inside the register and the status flag. the following table describes the information that can be obtained from each spi status flag: table 10. TIC12400-Q1 spi status flag description symbol name description por power-on reset this flag mirrors the por bit in the interrupt register int_stat, and it indicates, if set to 1, that a reset event has occurred. this bit is asserted after a successful power-on-reset, hardware reset, or software reset. refer to section device reset for more details. spi_fail spi error this flag mirrors the spi_fail bit in the interrupt register int_stat and it indicates, if set to 1, that the last spi slave in (si) transaction is invalid. to program a complete word, 32 bits of information must be entered into the device. the spi logic counts the number of bits clocked into the ic and enables data latching only if exactly 32 bits have been clocked in. in case the word length exceeds or does not meet the required size, the spi_fail bit, which mirrors its value to this spi_fail status flag, of the interrupt register int_stat will be set to 1 and the int pin will be asserted low. the data received will be considered invalid. once the int_stat register is read, its content will be cleared on the rising edge of cs. the spi_fail status flag, which mirrors the spi_fail bit in the int_stat register, will also be de-asserted. note the spi_fail bit is not flagged if sclk is not present. prty_fail parity fail this flag mirrors the prty_fail bit in the interrupt register int_stat and it indicates, if set to 1, that the last spi slave in (si) transaction has a parity error. the device uses odd parity. if the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. the int will be asserted low and the prty_fail bit in the interrupt register (int_stat) is flagged to logic 1, and the prty_fail status flag, which mirrors the prty_fail bit in the int_stat register, is also set to 1. once the int_stat register is read, its content will be cleared on the rising edge of cs. the prty_fail status flag, which mirrors the prty_fail bit in the int_stat register, will also be de-asserted. ssc switch state change this flag mirrors the ssc bit in the interrupt register int_stat and it indicates, if set to 1, that one or more switch inputs crossed a threshold. to determine the origin of the state change, the microcontroller can read the content of registers in_stat_comp (if input is set to comparator input mode), in_stat_adc0 to in_stat_adc1 (if input is set to adc input mode), or in_stat_matrix0 to in_stat_matrix1 (if input is set to matrix input). once the interrupt register (int_stat) is read, its content will be cleared on the rising edge of cs. the ssc status flag, which mirrors the ssc bit in the int_stat register, will also be de-asserted. vs_th v s threshold crossing this flag is set to 1 if either vs0 or vs1 bit in the interrupt register int_stat is flagged to 1. it indicates the v s voltage crosses one or more thresholds defined by vs0_thres2a, vs0_thres2b, vs1_thres2a, or vs1_thres2b. to determine the origin of the threshold crossing, the microcontroller can read register bits vs0_stat and vs1_stat in the register in_stat_misc. once the interrupt register (int_stat) is read, its content will be cleared on the rising edge of cs, and the vs_th status flag will also be de-asserted. temp temperature event this flag is set to 1 if either temperature warning (tw) or temperature shutdown (tsd) bit in the interrupt register int_stat is flagged to 1. it indicates a tw event or a tsd event has occurred. it is also flagged to 1 if a tw event or a tsd event is cleared. the interrupt register int_stat should be read to determine which event occurred. the spi master can also read the in_stat_misc register to get information on the temperature status of the device. once the interrupt register (int_stat) is read, its content will be cleared on the rising edge of cs, and the temp status flag will also be de-asserted. oi other interrupt other interrupt include interrupts such as ov, uv, crc_calc. wet_diag, adc_diag and chk_fail. this flag will be asserted 1 when any of the abovementioned bits is flagged in the interrupt register int_stat. the interrupt register int_stat should be read to determine which event(s) occurred. the spi master can also read the in_stat_misc register to get information on the latest status of the device. once the int_stat register is read, its content will be cleared on the rising edge of cs, and the oi status flag will also be de-asserted.
48 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6 register_maps table 11 lists the memory-mapped registers for the TIC12400-Q1. all register offset addresses not listed in table 11 should be considered as reserved locations and the register contents should not be modified. table 11. TIC12400-Q1 registers offset type reset acronym register name section 1h r 20h device_id device id register go 2h rc 1h int_stat interrupt status register go 3h r ffffh crc crc result register go 4h r 0h in_stat_misc miscellaneous status register go 5h r 0h in_stat_comp comparator status register go 6h-7h r 0h in_stat_adc0, in_stat_adc1 adc status register go 8h-9h r 0h in_stat_matrix0, in_stat_matrix1 matrix status register go ah-16h r 0h ana_stat0- ana_stat12 adc raw code register go 17h-19h ? ? reserved reserved ? 1ah r/w 0h config device global configuration register go 1bh r/w 0h in_en input enable register go 1ch r/w 0h cs_select current source/sink selection register go 1dh-1eh r/w 0h wc_cfg0, wc_cfg1 wetting current configuration register go 1fh-20h r/w 0h ccp_cfg0, ccp_cfg1 clean current polling register go 21h r/w 0h thres_comp comparator threshold control register go 22h-23h r/w 0h int_en_comp1, int_en_comp2 comparator input interrupt generation control register go 24h r/w 0h int_en_cfg0 global interrupt generation control register go 25h-28h r/w 0h int_en_cfg1- int_en_cfg4 adc input interrupt generation control register go 29h-2dh r/w 0h thres_cfg0- thres_cfg4 adc threshold control register go 2eh- 30h r/w 0h thresmap_cfg0- thresmap_cfg2 adc threshold mapping register go 31h r/w 0h matrix matrix setting register go 32h r/w 0h mode mode setting register go
49 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.1 device_id register (offset = 1h) [reset = 20h] device_id is shown in figure 38 and described in table 12 . return to summary table . this register represents the device id of the TIC12400-Q1. figure 38. device_id register 23 22 21 20 19 18 17 16 15 14 13 12 reserved r-0h 11 10 9 8 7 6 5 4 3 2 1 0 reserv ed major minor r-0h r-2h r-0h legend: r = read only table 12. device_id register field descriptions bit field type reset description 23-11 reserved r 0h reserved 10-4 major r 2h these 7 bits represents major revision id. for TIC12400-Q1 the major revision id is 2h. 3-0 minor r 0h these 4 bits represents minor revision id. for TIC12400-Q1 the minor revision id is 0h.
50 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.2 int_stat register (offset = 2h) [reset = 1h] int_stat is shown in figure 39 and described in table 13 . return to summary table . this register records the information of the event as it occurs in the device. a read command executed on this register clears its content and resets the register to its default value. the int pin is released at the rising edge of the cs pin from the read command. figure 39. int_stat register 23 22 21 20 19 18 17 16 reserved r-0h 15 14 13 12 11 10 9 8 reserved chk_fail adc_diag wet_diag vs1 vs0 crc_calc r-0h rc-0h rc-0h rc-0h rc-0h rc-0h rc-0h 7 6 5 4 3 2 1 0 uv ov tw tsd ssc prty_fail spi_fail por rc-0h rc-0h rc-0h rc-0h rc-0h rc-0h rc-0h rc-1h legend: r = read only; rc = read to clear table 13. int_stat register field descriptions bit field type reset description 23-14 reserved r 0h reserved 13 chk_fail rc 0h 0h = default factory setting is successfully loaded upon device initialization or the event status got cleared after a read command was executed on the int_stat register. 1h = an error is detected when loading factory settings into the device upon device initialization. during device initialization, factory settings are programmed into the device to allow proper device operation. the device performs a self- check after the device is programmed to diagnose whether correct settings are loaded. if the self-check returns an error, the chk_fail bit is flagged to logic 1 along with the por bit. the host controller is then recommended to initiate a software reset (see section software reset ) to re-initialize the device and allow correct settings to be re- programmed. 12 adc_diag rc 0h 0h = no adc self-diagnostic error is detected or the event status got cleared after a read command was executed on the int_stat register. 1h = adc self-diagnostic error is detected. the adc self-diagnostic feature (see section adc self-diagnostic ) can be activated to monitor the integrity of the internal adc. the adc_diag bit is flagged to logic 1 if an adc error is diagnosed. 11 wet_diag rc 0h 0h = no wetting current error is detected, or the event status got cleared after a read command was executed on the int_stat register. 1h = wetting current error is detected. the wetting current diagnostic feature (see section wetting current diagnostic ) can be activated to monitor the integrity of the internal current sources or sinks. the wet_diag bit is flagged to logic 1 if a wetting current error is diagnosed.
51 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 13. int_stat register field descriptions (continued) bit field type reset description 10 vs1 rc 0h 0h = no v s voltage state change occurred with respect to vs1_thres2a or vs1_thres2b or the status got cleared after a read command was executed on the int_stat register. 1h = v s voltage state change occurred with respect to vs1_thres2a or vs1_thres2b. the vs1 interrupt bit indicates whether v s voltage state change occurred with respect to thresholds vs1_thres2a and vs1_thres2b if the v s measurement feature (see section vs measurement ) is activated. 9 vs0 rc 0h 0h = no v s voltage state change occurred with respect to vs0_thres2a or vs0_thres2b or the status got cleared after a read command was executed on the int_stat register. 1h = v s voltage state change occurred with respect to vs0_thres2a or vs0_thres2b. the vs0 interrupt bit indicates whether v s voltage state change occurred with respect to thresholds vs0_thres2a and vs0_thres2b if the v s measurement feature (see section vs measurement ) is activated. 8 crc_calc rc 0h 0h = crc calculation is running, not started, or was acknowledged after a read command was executed on the int_stat register. 1h = crc calculation is finished. crc calculation (see section cyclic redundancy check (crc) ) can be triggered to make sure correct register values are programmed into the device. once the calculation is completed, the crc_calc bit is flagged to logic 1 to indicate completion of the calculation, and the result can then be accessed from the crc (offset = 3h) register. 7 uv rc 0h 0h = no under-voltage condition occurred or cleared on the v s pin, or the event status got cleared after a read command was executed on the int_stat register. 1h = under-voltage condition occurred or cleared on the v s pin. when the uv bit is flagged to logic 1, it indicates the under-voltage (uv) event has occurred. the bit is also flagged to logic 1 when the event clears. for more details about the uv operation, please refer to section vs under-voltage (uv) condition . 6 ov rc 0h 0h = no over-voltage condition occurred or cleared on the v s pin, or the event status got cleared after a read command was executed on the int_stat register. 1h = over-voltage condition occurred or cleared on the v s pin. when the ov bit is flagged to logic 1, it indicates the over-voltage (ov) event has occurred. the bit is also flagged to logic 1 when the event clears. for more details about the ov operation, please refer to section vs over-voltage (ov) condition . 5 tw rc 0h 0h = no temperature warning event occurred or the event status got cleared after a read command was executed on the int_stat register. 1h = temperature warning event occurred or cleared. when the tw bit is flagged to logic 1, it indicates the temperature warning event has occurred. the bit is also flagged to logic 1 when the event clears. for more details about the temperature warning operation, please refer to section temperature warning (tw)
52 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 13. int_stat register field descriptions (continued) bit field type reset description 4 tsd rc 0h 0h = no temperature shutdown event occurred or the event status got cleared after a read command was executed on the int_stat register. 1h = temperature shutdown event occurred or cleared. when the tsd bit is flagged to logic 1, it indicates the temperature shutdown event has occurred. the bit is also flagged to logic 1 when the event clears. for more details about the temperature shutdown operation, please refer to section temperature shutdown (tsd) 3 ssc rc 0h 0h = no switch state change occurred or the status got cleared after a read command was executed on the int_stat register. 1h = switch state change occurred. the switch state change (ssc) bit indicates whether input threshold crossing has occurred from switch inputs in0 to in23. this bit is also flagged to logic 1 after the first polling cycle is completed after device polling is triggered. 2 prty_fail rc 0h 0h = no parity error occurred in the last received si stream or the error status got cleared after a read command was executed on the int_stat register. 1h = parity error occurred. when the prty_fail bit is flagged to logic 1, it indicates the last spi slave in (si) transaction has a parity error. the device uses odd parity. if the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. the value of this register bit is mirrored to the prty_flag spi status flag. 1 spi_fail rc 0h 0h = 32 clock pulse during a cs = low sequence was detected or the error status got cleared after a read command was executed on the int_stat register. 1h = spi error occurred when the spi_fail bit is flagged to logic 1, it indicates the last spi slave in (si) transaction is invalid. to program a complete word, 32 bits of information must be entered into the device. the spi logic counts the number of bits clocked into the ic and enables data latching only if exactly 32 bits have been clocked in. in case the word length exceeds or does not meet the required length, the spi_fail bit is flagged to logic 1, and the data received is considered invalid. the value of this register bit is mirrored to the spi_flag spi status flag. note the spi_fail bit is not flagged if sclk is not present. 0 por rc 1h 0h = no power-on-reset (por) event occurred or the status got cleared after a read command was executed on the int_stat register. 1h = power-on-reset (por) event occurred. the power-on-reset (por) interrupt bit indicates whether a reset event has occurred. a reset event sets the registers to their default values and re-initializes the device state machine. this bit is asserted after a successful power-on-reset, hardware reset, or software reset. the value of this register bit is mirrored to the por spi status flag.
53 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.3 crc register (offset = 3h) [reset = ffffh] crc is shown in figure 40 and described in table 14 . return to summary table . this register returns the crc-16-cccit calculation result. the microcontroller can compare this value with its own calculated value to ensure correct register settings are programmed to the device. figure 40. crc register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved crc r-0h r-ffffh legend: r = read only table 14. crc register field descriptions bit field type reset description 23-16 reserved r 0h reserved 15-0 crc r ffffh crc-16-ccitt calculation result: bit1: lsb of crc bit16: msb or crc
54 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.4 in_stat_misc register (offset = 4h) [reset = 0h] in_stat_misc is shown in figure 41 and described in table 15 . return to summary table . this register indicates current device status unrelated to switch input monitoring. figure 41. in_stat_misc register 23 22 21 20 19 18 17 16 reserved r-0h 15 14 13 12 11 10 9 8 reserved adc_d in3_d in2_d in1_d in0_d r-0h r-0h r-0h r-0h r-0h r-0h 7 6 5 4 3 2 1 0 vs1_stat vs0_stat uv_stat ov_stat tw_stat tsd_stat r-0h r-0h r-0h r-0h r-0h r-0h table 15. in_stat_misc register field descriptions bit field type reset description 23-13 reserved r 0h reserved 12 adc_d r 0h 0h = no error is identified from adc self-diagnostic. 1h = an error is identified from adc self-diagnostic. 11 in3_d r 0h 0h = current sink on in3 is operational. 1h = current sink on in3 is abnormal. 10 in2_d r 0h 0h = current sink on in2 is operational. 1h = current sink on in2 is abnormal. 9 in1_d r 0h 0h = current source on in1 is operational. 1h = current source on in1 is abnormal. 8 in0_d r 0h 0h = current source on in0 is operational. 1h = current source on in0 is abnormal. 7-6 vs1_stat r 0h 0h = v s voltage is below threshold vs1_thres2a. 1h = v s voltage is below threshold vs1_thres2b and equal to or above threshold vs1_thres2a. 2h = v s voltage is equal to or above threshold vs1_thres2b. 3h = n/a. 5-4 vs0_stat r 0h 0h = v s voltage is below threshold vs0_thres2a. 1h = v s voltage is below threshold vs0_thres2b and equal to or above threshold vs0_thres2a. 2h = v s voltage is equal to or above threshold vs0_thres2b. 3h = n/a 3 uv_stat r 0h 0h = v s voltage is above the under-voltage condition threshold. 1h = v s voltage is below the under-voltage condition threshold. 2 ov_stat r 0h 0h = v s voltage is below the over-voltage condition threshold. 1h = v s voltage is above the over-voltage condition threshold. 1 tw_stat r 0h 0h = device junction temperature is below the temperature warning threshold t tw . 1h = device junction temperature is above the temperature warning threshold t tw .
55 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 15. in_stat_misc register field descriptions (continued) bit field type reset description 0 tsd_stat r 0h 0h = device junction temperature is below the temperature shutdown threshold t tsd . 1h = device junction temperature is above the temperature shutdown threshold t tsd .
56 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.5 in_stat_comp register (offset = 5h) [reset = 0h] in_stat_comp is shown in figure 42 and described in table 16 . return to summary table . this register indicates whether an input is below or above the comparator threshold when it is configured as comparator input mode. figure 42. in_stat_comp register 23 22 21 20 19 18 17 16 inc_23 inc_22 inc_21 inc_20 inc_19 inc_18 inc_17 inc_16 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h 15 14 13 12 11 10 9 8 inc_15 inc_14 inc_13 inc_12 inc_11 inc_10 inc_9 inc_8 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h 7 6 5 4 3 2 1 0 inc_7 inc_6 inc_5 inc_4 inc_3 inc_2 inc_1 inc_0 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h legend: r = read only table 16. in_stat_comp register field descriptions bit field type reset description 23 inc_23 r 0h 0h = input in23 is below the comparator threshold. 1h = input in23 is above the comparator threshold. 22 inc_22 r 0h 0h = input in22 is below the comparator threshold. 1h = input in22 is above the comparator threshold. 21 inc_21 r 0h 0h = input in21 is below the comparator threshold. 1h = input in21 is above the comparator threshold. 20 inc_20 r 0h 0h = input in20 is below the comparator threshold. 1h = input in20 is above the comparator threshold. 19 inc_19 r 0h 0h = input in19 is below the comparator threshold. 1h = input in19 is above the comparator threshold. 18 inc_18 r 0h 0h = input in18 is below the comparator threshold. 1h = input in18 is above the comparator threshold. 17 inc_17 r 0h 0h = input in17 is below the comparator threshold. 1h = input in17 is above the comparator threshold. 16 inc_16 r 0h 0h = input in16 is below the comparator threshold. 1h = input in16 is above the comparator threshold. 15 inc_15 r 0h 0h = input in15 is below the comparator threshold. 1h = input in15 is above the comparator threshold. 14 inc_14 r 0h 0h = input in14 is below the comparator threshold. 1h = input in14 is above the comparator threshold. 13 inc_13 r 0h 0h = input in13 is below the comparator threshold. 1h = input in13 is above the comparator threshold. 12 inc_12 r 0h 0h = input in12 is below the comparator threshold. 1h = input in12 is above the comparator threshold. 11 inc_11 r 0h 0h = input in11 is below the comparator threshold. 1h = input in11 is above the comparator threshold. 10 inc_10 r 0h 0h = input in10 is below the comparator threshold. 1h = input in10 is above the comparator threshold.
57 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 16. in_stat_comp register field descriptions (continued) bit field type reset description 9 inc_9 r 0h 0h = input in9 is below the comparator threshold. 1h = input in9 is above the comparator threshold. 8 inc_8 r 0h 0h = input in8 is below the comparator threshold. 1h = input in8 is above the comparator threshold. 7 inc_7 r 0h 0h = input in7 is below the comparator threshold. 1h = input in7 is above the comparator threshold. 6 inc_6 r 0h 0h = input in6 is below the comparator threshold. 1h = input in6 is above the comparator threshold. 5 inc_5 r 0h 0h = input in5 is below the comparator threshold. 1h = input in5 is above the comparator threshold. 4 inc_4 r 0h 0h = input in4 is below the comparator threshold. 1h = input in4 is above the comparator threshold. 3 inc_3 r 0h 0h = input in3 is below the comparator threshold. 1h = input in3 is above the comparator threshold. 2 inc_2 r 0h 0h = input in2 is below the comparator threshold. 1h = input in2 is above the comparator threshold. 1 inc_1 r 0h 0h = input in1 is below the comparator threshold. 1h = input in1 is above the comparator threshold. 0 inc_0 r 0h 0h = input in0 is below the comparator threshold. 1h = input in0 is above the comparator threshold.
58 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.6 in_stat_adc0 register (offset = 6h) [reset = 0h] in_stat_adc0 is shown in figure 43 and described in table 17 . return to summary table . this register indicates whether an input is below or above the programmed threshold (for in0-in11) when it is configured as adc input mode. for in12-in17, there are 2 thresholds and the register bits indicate whether the input is below, above or in-between the 2 thresholds. figure 43. in_stat_adc0 register 23 22 21 20 19 18 17 16 ina_17 ina_16 ina_15 ina_14 r-0h r-0h r-0h r-0h 15 14 13 12 11 10 9 8 ina_13 ina_12 ina_11 ina_10 ina_9 ina_8 r-0h r-0h r-0h r-0h r-0h r-0h 7 6 5 4 3 2 1 0 ina_7 ina_6 ina_5 ina_4 ina_3 ina_2 ina_1 ina_0 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h legend: r = read only table 17. in_stat_adc0 register field descriptions bit field type reset description 23-22 ina_17 r 0h 0h = input in17 is below threshold 2a. 1h = input in17 is below threshold 2b and equal to or above threshold 2a. 2h = input in17 is equal to or above threshold 2b. 3h = n/a 21-20 ina_16 r 0h 0h = input in16 is below threshold 2a. 1h = input in16 is below threshold 2b and equal to or above threshold 2a. 2h = input in16 is equal to or above threshold 2b. 3h = n/a 19-18 ina_15 r 0h 0h = input in15 is below threshold 2a. 1h = input in15 is below threshold 2b and equal to or above threshold 2a. 2h = input in15 is equal to or above threshold 2b. 3h = n/a 17-16 ina_14 r 0h 0h = input in14 is below threshold 2a. 1h = input in14 is below threshold 2b and equal to or above threshold 2a. 2h = input in14 is equal to or above threshold 2b. 3h = n/a 15-14 ina_13 r 0h 0h = input in13 is below threshold 2a. 1h = input in13 is below threshold 2b and equal to or above threshold 2a. 2h = input in13 is equal to or above threshold 2b. 3h = n/a 13-12 ina_12 r 0h 0h = input in12 is below threshold 2a. 1h = input in12 is below threshold 2b and equal to or above threshold 2a. 2h = input in12 is equal to or above threshold 2b. 3h = n/a
59 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 17. in_stat_adc0 register field descriptions (continued) bit field type reset description 11 ina_11 r 0h 0h = input in11 is below configured threshold. 1h = input in11 is above configured threshold. 10 ina_10 r 0h 0h = input in10 is below configured threshold. 1h = input in10 is above configured threshold. 9 ina_9 r 0h 0h = input in9 is below configured threshold. 1h = input in9 is above configured threshold. 8 ina_8 r 0h 0h = input in8 is below configured threshold. 1h = input in8 is above configured threshold. 7 ina_7 r 0h 0h = input in7 is below configured threshold. 1h = input in7 is above configured threshold. 6 ina_6 r 0h 0h = input in6 is below configured threshold. 1h = input in6 is above configured threshold. 5 ina_5 r 0h 0h = input in5 is below configured threshold. 1h = input in5 is above configured threshold. 4 ina_4 r 0h 0h = input in4 is below configured threshold. 1h = input in4 is above configured threshold. 3 ina_3 r 0h 0h = input in3 is below configured threshold. 1h = input in3 is above configured threshold. 2 ina_2 r 0h 0h = input in2 is below configured threshold. 1h = input in2 is above configured threshold. 1 ina_1 r 0h 0h = input in1 is below configured threshold. 1h = input in1 is above configured threshold. 0 ina_0 r 0h 0h = input in0 is below configured threshold. 1h = input in0 is above configured threshold.
60 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.7 in_stat_adc1 register (offset = 7h) [reset = 0h] in_stat_adc1 is shown in figure 44 and described in table 18 . return to summary table . this register indicates whether an input is above or below the programmed thresholds 3a, 3b, and 3c when it is configured as adc input mode. for in23, there are 5 thresholds that can be programmed. figure 44. in_stat_adc1 register 23 22 21 20 19 18 17 16 15 14 13 12 reserved ina_23 r-0h r-0h 11 10 9 8 7 6 5 4 3 2 1 0 ina_23 ina_22 ina_21 ina_20 ina_19 ina_18 r-0h r-0h r-0h r-0h r-0h r-0h legend: r = read only table 18. in_stat_adc1 register field descriptions bit field type reset description 23-13 reserved r 0h reserved 12-10 ina_23 r 0h 0h = input in23 is below threshold 3a. 1h = input in23 is below threshold 3b and equal to or above threshold 3a. 2h = input in23 is below threshold 3c and equal to or above threshold 3b. 3h = input in23 is below threshold thres8 and equal to or above threshold 3c. 4h = input in23 is below threshold thres9 and equal to or above threshold thres8. 5h = input in23 is equal to or above threshold thres9. 9-8 ina_22 r 0h 0h = input in22 is below threshold 3a. 1h = input in22 is below threshold 3b and equal to or above threshold 3a. 2h = input in22 is below threshold 3c and equal to or above threshold 3b. 3h = input in22 is equal to or above threshold 3c. 7-6 ina_21 r 0h 0h = input in21 is below threshold 3a. 1h = input in21 is below threshold 3b and equal to or above threshold 3a. 2h = input in21 is below threshold 3c and equal to or above threshold 3b. 3h = input in21 is equal to or above threshold 3c. 5-4 ina_20 r 0h 0h = input in20 is below threshold 3a. 1h = input in20 is below threshold 3b and equal to or above threshold 3a. 2h = input in20 is below threshold 3c and equal to or above threshold 3b. 3h = input in20 is equal to or above threshold 3c. 3-2 ina_19 r 0h 0h = input in19 is below threshold 3a. 1h = input in19 is below threshold 3b and equal to or above threshold 3a. 2h = input in19 is below threshold 3c and equal to or above threshold 3b. 3h = input in19 is equal to or above threshold 3c.
61 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 18. in_stat_adc1 register field descriptions (continued) bit field type reset description 1-0 ina_18 r 0h 0h = input is in18 is below threshold 3a. 1h = input is in18 is below threshold 3b and equal to or above threshold 3a. 2h = input is in18 is below threshold 3c and equal to or above threshold 3b. 3h = input is in18 is equal to or above threshold 3c.
62 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.8 in_stat_matrix0 register (offset = 8h) [reset = 0h] in_stat_matrix0 is shown in figure 45 and described in table 19 . return to summary table . this register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to in10-in13. figure 45. in_stat_matrix0 register 23 22 21 20 19 18 17 16 inmat_13_in9 inmat_13_in8 inmat_13_in7 inmat_13_in6 inmat_13_in5 inmat_13_in4 inmat_12_in9 inmat_12_in8 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h 15 14 13 12 11 10 9 8 inmat_12_in7 inmat_12_in6 inmat_12_in5 inmat_12_in4 inmat_11_in9 inmat_11_in8 inmat_11_in7 inmat_11_in6 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h 7 6 5 4 3 2 1 0 inmat_11_in5 inmat_11_in4 inmat_10_in9 inmat_10_in8 inmat_10_in7 inmat_10_in6 inmat_10_in5 inmat_10_in4 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h legend: r = read only table 19. in_stat_matrix0 register field descriptions bit field type reset description 23 inmat_13_in9 r 0h 0h = input in13 is below threshold while in9 pulled to gnd. 1h = input in13 is above threshold while in9 pulled to gnd. 22 inmat_13_in8 r 0h 0h = input in13 is below threshold while in8 pulled to gnd. 1h = input in13 is above threshold while in8 pulled to gnd. 21 inmat_13_in7 r 0h 0h = input in13 is below threshold while in7 pulled to gnd. 1h = input in13 is above threshold while in7 pulled to gnd. 20 inmat_13_in6 r 0h 0h = input in13 is below threshold while in6 pulled to gnd. 1h = input in13 is above threshold while in6 pulled to gnd. 19 inmat_13_in5 r 0h 0h = input in13 is below threshold while in5 pulled to gnd. 1h = input in13 is above threshold while in5 pulled to gnd. 18 inmat_13_in4 r 0h 0h = input in13 is below threshold while in4 pulled to gnd. 1h = input in13 is above threshold while in4 pulled to gnd. 17 inmat_12_in9 r 0h 0h = input in12 is below threshold while in9 pulled to gnd. 1h = input in12 is above threshold while in9 pulled to gnd. 16 inmat_12_in8 r 0h 0h = input in12 is below threshold while in8 pulled to gnd. 1h = input in12 is above threshold while in8 pulled to gnd. 15 inmat_12_in7 r 0h 0h = input in12 is below threshold while in7 pulled to gnd. 1h = input in12 is above threshold while in7 pulled to gnd. 14 inmat_12_in6 r 0h 0h = input in12 is below threshold while in6 pulled to gnd. 1h = input in12 is above threshold while in6 pulled to gnd. 13 inmat_12_in5 r 0h 0h = input in12 is below threshold while in5 pulled to gnd. 1h = input in12 is above threshold while in5 pulled to gnd. 12 inmat_12_in4 r 0h 0h = input in12 is below threshold while in4 pulled to gnd. 1h = input in12 is above threshold while in4 pulled to gnd. 11 inmat_11_in9 r 0h 0h = input in11 is below threshold while in9 pulled to gnd. 1h = input in11 is above threshold while in9 pulled to gnd. 10 inmat_11_in8 r 0h 0h = input in11 is below threshold while in8 pulled to gnd. 1h = input in11 is above threshold while in8 pulled to gnd.
63 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 19. in_stat_matrix0 register field descriptions (continued) bit field type reset description 9 inmat_11_in7 r 0h 0h = input in11 is below threshold while in7 pulled to gnd. 1h = input in11 is above threshold while in7 pulled to gnd. 8 inmat_11_in6 r 0h 0h = input in11 is below threshold while in6 pulled to gnd. 1h = input in11 is above threshold while in6 pulled to gnd. 7 inmat_11_in5 r 0h 0h = input in11 is below threshold while in5 pulled to gnd. 1h = input in11 is above threshold while in5 pulled to gnd. 6 inmat_11_in4 r 0h 0h = input in11 is below threshold while in4 pulled to gnd. 1h = input in11 is above threshold while in4 pulled to gnd. 5 inmat_10_in9 r 0h 0h = input in10 is below threshold while in9 pulled to gnd. 1h = input in10 is above threshold while in9 pulled to gnd. 4 inmat_10_in8 r 0h 0h = input in10 is below threshold while in8 pulled to gnd. 1h = input in10 is above threshold while in8 pulled to gnd. 3 inmat_10_in7 r 0h 0h = input in10 is below threshold while in7 pulled to gnd. 1h = input in10 is above threshold while in7 pulled to gnd. 2 inmat_10_in6 r 0h 0h = input in10 is below threshold while in6 pulled to gnd. 1h = input in10 is above threshold while in6 pulled to gnd. 1 inmat_10_in5 r 0h 0h = input in10 is below threshold while in5 pulled to gnd. 1h = input in10 is above threshold while in5 pulled to gnd. 0 inmat_10_in4 r 0h 0h = input in10 is below threshold while in4 pulled to gnd. 1h = input in10 is above threshold while in4 pulled to gnd.
64 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.9 in_stat_matrix1 register (offset = 9h) [reset = 0h] in_stat_matrix1 is shown in figure 46 and described in table 20 . return to summary table . this register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to in14-in15. this register also indicates the status of in0-in11 with respect to. the common threshold thres_com. figure 46. in_stat_matrix1 register 23 22 21 20 19 18 17 16 in11_com in10_com in9_com in8_com in7_com in6_com in5_com in4_com r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h 15 14 13 12 11 10 9 8 in3_com in2_com in1_com in0_com inmat_15_in9 inmat_15_in8 inmat_15_in7 inmat_15_in6 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h 7 6 5 4 3 2 1 0 inmat_15_in5 inmat_15_in4 inmat_14_in9 inmat_14_in8 inmat_14_in7 inmat_14_in6 inmat_14_in5 inmat_14_in4 r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h legend: r = read only table 20. in_stat_matrix1 register field descriptions bit field type reset description 23 in11_com r 0h 0h = input in11 below threshold thres_com 1h = input in11 equal to or above threshold thres_com 22 in10_com r 0h 0h = input in10 below threshold thres_com 1h = input in10 equal to or above threshold thres_com 21 in9_com r 0h 0h = input in9 below threshold thres_com 1h = input in9 equal to or above threshold thres_com 20 in8_com r 0h 0h = input in8 below threshold thres_com 1h = input in8 equal to or above threshold thres_com 19 in7_com r 0h 0h = input in7 below threshold thres_com 1h = input in7 equal to or above threshold thres_com 18 in6_com r 0h 0h = input in6 below threshold thres_com 1h = input in6 equal to or above threshold thres_com 17 in5_com r 0h 0h = input in5 below threshold thres_com 1h = input in5 equal to or above threshold thres_com 16 in4_com r 0h 0h = input in4 below threshold thres_com 1h = input in4 equal to or above threshold thres_com 15 in3_com r 0h 0h = input in3 below threshold thres_com 1h = input in3 equal to or above threshold thres_com 14 in2_com r 0h 0h = input in2 below threshold thres_com 1h = input in2 equal to or above threshold thres_com 13 in1_com r 0h 0h = input in1 below threshold thres_com 1h = input in1 equal to or above threshold thres_com 12 in0_com r 0h 0h = input in0 below threshold thres_com 1h = input in0 equal to or above threshold thres_com 11 inmat_15_in9 r 0h 0h = input in15 below threshold while in9 pulled to gnd 1h = input in15 above threshold while in9 pulled to gnd
65 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 20. in_stat_matrix1 register field descriptions (continued) bit field type reset description 10 inmat_15_in8 r 0h 0h = input in15 below threshold while in8 pulled to gnd 1h = input in15 above threshold while in8 pulled to gnd 9 inmat_15_in7 r 0h 0h = input in15 below threshold while in7 pulled to gnd 1h = input in15 above threshold while in7 pulled to gnd 8 inmat_15_in6 r 0h 0h = input in15 below threshold while in6 pulled to gnd 1h = input in15 above threshold while in6 pulled to gnd 7 inmat_15_in5 r 0h 0h = input in15 below threshold while in5 pulled to gnd 1h = input in15 above threshold while in5 pulled to gnd 6 inmat_15_in4 r 0h 0h = input in15 below threshold while in4 pulled to gnd 1h = input in15 above threshold while in4 pulled to gnd 5 inmat_14_in9 r 0h 0h = input in14 below threshold while in9 pulled to gnd 1h = input in14 above threshold while in9 pulled to gnd 4 inmat_14_in8 r 0h 0h = input in14 below threshold while in8 pulled to gnd 1h = input in14 above threshold while in8 pulled to gnd 3 inmat_14_in7 r 0h 0h = input in14 below threshold while in7 pulled to gnd 1h = input in14 above threshold while in7 pulled to gnd 2 inmat_14_in6 r 0h 0h = input in14 below threshold while in6 pulled to gnd 1h = input in14 above threshold while in6 pulled to gnd 1 inmat_14_in5 r 0h 0h = input in14 below threshold while in5 pulled to gnd 1h = input in14 above threshold while in5 pulled to gnd 0 inmat_14_in4 r 0h 0h = input in14 below threshold while in4 pulled to gnd 1h = input in14 above threshold while in4 pulled to gnd
66 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.10 ana_stat0 register (offset = ah) [reset = 0h] ana_stat0 is shown in figure 47 and described in table 21 . return to summary table . figure 47. ana_stat0 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in1_ana in0_ana r-0h r-0h r-0h legend: r = read only table 21. ana_stat0 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in1_ana r 0h 10-bits value of in1 bit 10: lsb bit 19: msb 9-0 in0_ana r 0h 10-bits value of in0 bit 0: lsb bit 9: msb 8.6.11 ana_stat1 register (offset = bh) [reset = 0h] ana_stat1 is shown in figure 48 and described in table 22 . return to summary table . figure 48. ana_stat1 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in5_ana in4_ana r-0h r-0h r-0h legend: r = read only table 22. ana_stat1 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in3_ana r 0h 10-bits value of in3 bit 10: lsb bit 19: msb 9-0 in2_ana r 0h 10-bits value of in2 bit 0: lsb bit 9: msb
67 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.12 ana_stat2 register (offset = ch) [reset = 0h] ana_stat2 is shown in figure 49 and described in table 23 . return to summary table . figure 49. ana_stat2 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in5_ana in4_ana r-0h r-0h r-0h legend: r = read only table 23. ana_stat2 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in5_ana r 0h 10-bits value of in5 bit 10: lsb bit 19: msb 9-0 in4_ana r 0h 10-bits value of in4 bit 0: lsb bit 9: msb 8.6.13 ana_stat3 register (offset = dh) [reset = 0h] ana_stat3 is shown in figure 50 and described in table 24 . return to summary table . figure 50. ana_stat3 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in7_ana in6_ana r-0h r-0h r-0h legend: r = read only table 24. ana_stat3 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in7_ana r 0h 10-bits value of in7 bit 10: lsb bit 19: msb 9-0 in6_ana r 0h 10-bits value of in6 bit 0: lsb bit 9: msb
68 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.14 ana_stat4 register (offset = eh) [reset = 0h] ana_stat4 is shown in figure 51 and described in table 25 . return to summary table . figure 51. ana_stat4 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in9_ana in8_ana r-0h r-0h r-0h legend: r = read only table 25. ana_stat4 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in9_ana r 0h 10-bits value of in9 bit 10: lsb bit 19: msb 9-0 in8_ana r 0h 10-bits value of in8 bit 0: lsb bit 9: msb 8.6.15 ana_stat5 register (offset = fh) [reset = 0h] ana_stat5 is shown in figure 52 and described in table 26 . return to summary table . figure 52. ana_stat5 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in11_ana in10_ana r-0h r-0h r-0h legend: r = read only table 26. ana_stat5 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in11_ana r 0h 10-bits value of in11 bit 10: lsb bit 19: msb 9-0 in10_ana r 0h 10-bits value of in10 bit 0: lsb bit 9: msb
69 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.16 ana_stat6 register (offset = 10h) [reset = 0h] ana_stat6 is shown in figure 53 and described in table 27 . return to summary table . figure 53. ana_stat6 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in13_ana in12_ana r-0h r-0h r-0h legend: r = read only table 27. ana_stat6 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in13_ana r 0h 10-bits value of in13 bit 10: lsb bit 19: msb 9-0 in12_ana r 0h 10-bits value of in12 bit 0: lsb bit 9: msb 8.6.17 ana_stat7 register (offset = 11h) [reset = 0h] ana_stat7 is shown in figure 54 and described in table 28 . return to summary table . figure 54. ana_stat7 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in15_ana in14_ana r-0h r-0h r-0h legend: r = read only table 28. ana_stat7 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in15_ana r 0h 10-bits value of in15 bit 10: lsb bit 19: msb 9-0 in14_ana r 0h 10-bits value of in14 bit 0: lsb bit 9: msb
70 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.18 ana_stat8 register (offset = 12h) [reset = 0h] ana_stat8 is shown in figure 55 and described in table 29 . return to summary table . figure 55. ana_stat8 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in17_ana in16_ana r-0h r-0h r-0h legend: r = read only table 29. ana_stat8 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in17_ana r 0h 10-bits value of in17 bit 10: lsb bit 19: msb 9-0 in16_ana r 0h 10-bits value of in16 bit 0: lsb bit 9: msb 8.6.19 ana_stat9 register (offset = 13h) [reset = 0h] ana_stat9 is shown in figure 56 and described in table 30 . return to summary table . figure 56. ana_stat9 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in19_ana in18_ana r-0h r-0h r-0h legend: r = read only table 30. ana_stat9 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in19_ana r 0h 10-bits value of in19 bit 10: lsb bit 19: msb 9-0 in18_ana r 0h 10-bits value of in18 bit 0: lsb bit 9: msb
71 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.20 ana_stat10 register (offset = 14h) [reset = 0h] ana_stat10 is shown in figure 57 and described in table 31 . return to summary table . figure 57. ana_stat10 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in21_ana in20_ana r-0h r-0h r-0h legend: r = read only table 31. ana_stat10 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in21_ana r 0h 10-bits value of in21 bit 10: lsb bit 19: msb 9-0 in20_ana r 0h 10-bits value of in20 bit 0: lsb bit 9: msb 8.6.21 ana_stat11 register (offset = 15h) [reset = 0h] ana_stat11 is shown in figure 58 and described in table 32 . return to summary table . figure 58. ana_stat11 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved in23_ana in22_ana r-0h r-0h r-0h legend: r = read only table 32. ana_stat11 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 in23_ana r 0h 10-bits value of in23 bit 10: lsb bit 19: msb 9-0 in22_ana r 0h 10-bits value of in22 bit 0: lsb bit 9: msb
72 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.22 ana_stat12 register (offset = 16h) [reset = 0h] ana_stat12 is shown in figure 59 and described in table 33 . return to summary table . figure 59. ana_stat12 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved adc_self_ana v s _ana r-0h r-0h r-0h legend: r = read only table 33. ana_stat12 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 adc_self_ana r 0h 10-bits value of the adc self-diagnosis bit 10: lsb bit 19: msb 9-0 v s _ana r 0h 10-bits value of v s measurement bit 0: lsb bit 9: msb
73 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.23 config register (offset = 1ah) [reset = 0h] config is shown in figure 60 and described in table 34 . return to summary table . figure 60. config register 23 22 21 20 19 18 17 16 vs_ratio adc_diag_t wet_d_in3_e n wet_d_in2_e n wet_d_in1_e n wet_d_in0_e n vs_meas_en tw_cur_dis_ csi r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 15 14 13 12 11 10 9 8 det_filter tw_cur_dis_ cso int_config trigger poll_en crc_t poll_act_ti me r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 7 6 5 4 3 2 1 0 poll_act_time poll_time reset r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 34. config register field descriptions bit field type reset description 23 vs_ratio r/w 0h 0h = use voltage divider factor of 3 for the v s measurement 1h = use voltage divider factor of 10 for the v s measurement 22 adc_diag_t r/w 0h for detailed descriptions for the adc self-diagnostic feature, refer to section adc self-diagnostic 0h = disable adc self-diagnostic feature 1h = enable adc self-diagnostic feature 21 wet_d_in3_en r/w 0h 0h = disable wetting current diagnostic for input in3 1h = enable wetting current diagnostic for input in3 20 wet_d_in2_en r/w 0h 0h = disable wetting current diagnostic for input in2 1h = enable wetting current diagnostic for input in2 19 wet_d_in1_en r/w 0h 0h = disable wetting current diagnostic for input in1 1h = enable wetting current diagnostic for input in1 18 wet_d_in0_en r/w 0h 0h = disable wetting current diagnostic for input in0 1h = enable wetting current diagnostic for input in0 17 vs_meas_en r/w 0h for detailed descriptions for the v s measurement, refer to section vs measurement . 0h = disable v s measurement at the end of every polling cycle 1h = enable v s measurement at the end of every polling cycle 16 tw_cur_dis_csi r/w 0h 0h = enable wetting current reduction (to 2 ma) for 10ma and 15ma settings upon tw event for all inputs enabled with csi. 1h = disable wetting current reduction (to 2 ma) for 10ma and 15ma settings upon tw event for all inputs enabled with csi. 15-14 det_filter r/w 0h for detailed descriptions for the detection filter, refer to section detection filter . 0h = every sample is valid and taken for threshold evaluation 1h = 2 consecutive and equal samples required to be valid data 2h = 3 consecutive and equal samples required to be valid data 3h = 4 consecutive and equal samples required to be valid data 13 tw_cur_dis_cso r/w 0h 0h = enable wetting current reduction (to 2ma) for 10ma and 15ma settings upon tw event for all inputs enabled with cso. 1h = disable wetting current reduction (to 2ma) for 10ma and 15ma settings upon tw event for all inputs enabled with cso.
74 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 34. config register field descriptions (continued) bit field type reset description 12 int_config r/w 0h for detailed descriptions for the int pin assertion scheme, refer to section interrupt generation and /int assertion . 0h = int pin assertion scheme set to static 1h = int pin assertion scheme set to dynamic 11 trigger r/w 0h when the trigger bit is set to logic 1, normal device operation (wetting current activation and polling) starts. to stop device operation and keep the device in an idle state, de-assert this bit to 0. after device normal operation is triggered, if at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit trigger to logic 0 to stop device operation. once the re-configuration is completed, the microcontroller can set the trigger bit back to logic 1 to re-start device operation. if re- configuration is done on the fly without first stopping the device operation, false switch status could be reported and accidental interrupt might be issued. the following register bits are the exception and can be configured when trigger bit is set to logic 1: ? trigger (bit 11 of the config register) ? crc_t (bit 9 of the config register) ? reset (bit 0 of the config register) ? the ccp_cfg1 register 0h = stop TIC12400-Q1 from normal operation. 1h = trigger TIC12400-Q1 normal operation 10 poll_en r/w 0h 0h = polling disabled. device operates in continuous mode. 1h = polling enabled and the device operates in one of the polling modes. 9 crc_t r/w 0h set this bit to 1 to trigger a crc calculation on all the configuration register bits. once triggered, it is strongly recommended the spi master does not change the content of the configuration registers until the crc calculation is completed to avoid erroneous crc calculation result. the TIC12400-Q1 sets the crc_calc interrupt bit and asserts the int pin low when the crc calculation is completed. the calculated result will be available in the crc register. this bit self-clears back to 0 after crc calculation is executed. 0h = no crc calculation triggered 1h = trigger crc calculation 8-5 poll_act_time r/w 0h 0h = 64 s 1h = 128 s 2h = 192 s 3h = 256 s 4h = 320 s 5h = 384 s 6h = 448 s 7h = 512 s 8h = 640 s 9h = 768 s ah = 896 s bh = 1024 s ch = 2048 s dh-15h = 512 s (most frequently-used setting)
75 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 34. config register field descriptions (continued) bit field type reset description 4-1 poll_time r/w 0h 0h = 2ms 1h = 4ms 2h = 8ms 3h = 16ms 4h = 32ms 5h = 48ms 6h = 64ms 7h = 128ms 8h = 256ms 9h = 512ms ah = 1024ms bh = 2048ms ch = 4096ms dh-15h = 8ms (most frequently-used setting) 0 reset r/w 0h 0h = no reset 1h = trigger software reset of the device.
76 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.24 in_en register (offset = 1bh) [reset = 0h] in_en is shown in figure 61 and described in table 35 . return to summary table . figure 61. in_en register 23 22 21 20 19 18 17 16 in_en_23 in_en_22 in_en_21 in_en_20 in_en_19 in_en_18 in_en_17 in_en_16 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 15 14 13 12 11 10 9 8 in_en_15 in_en_14 in_en_13 in_en_12 in_en_11 in_en_10 in_en_9 in_en_8 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 7 6 5 4 3 2 1 0 in_en_7 in_en_6 in_en_5 in_en_4 in_en_3 in_en_2 in_en_1 in_en_0 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 35. in_en register field descriptions bit field type reset description 23 in_en_23 r/w 0h 0h = input channel in23 disabled. polling sequence skips this channel 1h = input channel in23 enabled. 22 in_en_22 r/w 0h 0h = input channel in22 disabled. polling sequence skips this channel 1h = input channel in22 enabled. 21 in_en_21 r/w 0h 0h = input channel in21 disabled. polling sequence skips this channel 1h = input channel in21 enabled. 20 in_en_20 r/w 0h 0h = input channel in20 disabled. polling sequence skips this channel 1h = input channel in20 enabled. 19 in_en_19 r/w 0h 0h = input channel in19 disabled. polling sequence skips this channel 1h = input channel in19 enabled. 18 in_en_18 r/w 0h 0h = input channel in18 disabled. polling sequence skips this channel 1h = input channel in18 enabled. 17 in_en_17 r/w 0h 0h = input channel in17 disabled. polling sequence skips this channel 1h = input channel in17 enabled. 16 in_en_16 r/w 0h 0h = input channel in16 disabled. polling sequence skips this channel 1h = input channel in16 enabled. 15 in_en_15 r/w 0h 0h = input channel in15 disabled. polling sequence skips this channel 1h = input channel in15 enabled. 14 in_en_14 r/w 0h 0h = input channel in14 disabled. polling sequence skips this channel 1h = input channel in14 enabled. 13 in_en_13 r/w 0h 0h = input channel in13 disabled. polling sequence skips this channel 1h = input channel in13 enabled.
77 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 35. in_en register field descriptions (continued) bit field type reset description 12 in_en_12 r/w 0h 0h = input channel in12 disabled. polling sequence skips this channel 1h = input channel in12 enabled. 11 in_en_11 r/w 0h 0h = input channel in11 disabled. polling sequence skips this channel 1h = input channel in11 enabled. 10 in_en_10 r/w 0h 0h = input channel in10 disabled. polling sequence skips this channel 1h = input channel in10 enabled. 9 in_en_9 r/w 0h 0h = input channel in9 disabled. polling sequence skips this channel 1h = input channel in9 enabled. 8 in_en_8 r/w 0h 0h = input channel in8 disabled. polling sequence skips this channel 1h = input channel in8 enabled. 7 in_en_7 r/w 0h 0h = input channel in7 disabled. polling sequence skips this channel 1h = input channel in7 enabled. 6 in_en_6 r/w 0h 0h = input channel in6 disabled. polling sequence skips this channel 1h = input channel in6 enabled. 5 in_en_5 r/w 0h 0h = input channel in5 disabled. polling sequence skips this channel 1h = input channel in5 enabled. 4 in_en_4 r/w 0h 0h = input channel in4 disabled. polling sequence skips this channel 1h = input channel in4 enabled. 3 in_en_3 r/w 0h 0h = input channel in3 disabled. polling sequence skips this channel 1h = input channel in3 enabled. 2 in_en_2 r/w 0h 0h = input channel in2 disabled. polling sequence skips this channel 1h = input channel in2 enabled. 1 in_en_1 r/w 0h 0h = input channel in1 disabled. polling sequence skips this channel 1h = input channel in1 enabled. 0 in_en_0 r/w 0h 0h = input channel in0 disabled. polling sequence skips this channel 1h = input channel in0 enabled.
78 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.25 cs_select register (offset = 1ch) [reset = 0h] cs_select is shown in figure 62 and described in table 36 . return to summary table . figure 62. cs_select register 23 22 21 20 19 18 17 16 15 14 13 12 reserved r-0h 11 10 9 8 7 6 5 4 3 2 1 0 reserved cs_in9 cs_in8 cs_in7 cs_in6 cs_in5 cs_in4 cs_in3 cs_in2 cs_in1 cs_in0 r-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only table 36. cs_select register field descriptions bit field type reset description 23-10 reserved r 0h reserved 9 cs_in9 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 8 cs_in8 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 7 cs_in7 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 6 cs_in6 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 5 cs_in5 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 4 cs_in4 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 3 cs_in3 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 2 cs_in2 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 1 cs_in1 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected 0 cs_in0 r/w 0h 0h = current source (cso) selected 1h = current sink (csi) selected
79 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.26 wc_cfg0 register (offset = 1dh) [reset = 0h] wc_cfg0 is shown in figure 63 and described in table 37 . return to summary table . figure 63. wc_cfg0 register 23 22 21 20 19 18 17 16 15 14 13 12 wc_in11 wc_in10 wc_in8_in9 wc_in6_in7 r/w-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 wc_in5 wc_in4 wc_in2_in3 wc_in0_in1 r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 37. wc_cfg0 register field descriptions bit field type reset description 23-21 wc_in11 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 20-18 wc_in10 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 17-15 wc_in8_in9 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 14-12 wc_in6_in7 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 11-9 wc_in5 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 8-6 wc_in4 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current
80 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 37. wc_cfg0 register field descriptions (continued) bit field type reset description 5-3 wc_in2_in3 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 2-0 wc_in0_in1 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current
81 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.27 wc_cfg1 register (offset = 1eh) [reset = 0h] wc_cfg1 is shown in figure 64 and described in table 38 . return to summary table . figure 64. wc_cfg1 register 23 22 21 20 19 18 17 16 15 14 13 12 reserv ed auto_s cale_di s_csi auto_s cale_di s_cso wc_in23 wc_in22 wc_in20_in21 r-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 wc_in18_in19 wc_in16_in17 wc_in14_in15 wc_in12_in13 r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only table 38. wc_cfg1 register field descriptions bit field type reset description 24-23 reserved r 0h reserved 22 auto_scale_dis_csi r/w 0h 0h = enable wetting current auto-scaling (to 2ma) in continuous mode for 10ma and 15ma settings upon switch closure for all inputs enabled with csi 1h = disable wetting current auto-scaling (to 2ma) in continuous mode for 10ma and 15ma settings upon switch closure for all inputs enabled with cs for detailed descriptions for the wetting current auto-scaling, refer to section wetting current auto-scaling . 21 auto_scale_dis_cso r/w 0h 0h = enable wetting current auto-scaling (to 2ma) in continuous mode for 10ma and 15ma settings upon switch closure for all inputs enabled with cso 1h = disable wetting current auto-scaling (to 2ma) in continuous mode for 10ma and 15ma settings upon switch closure for all inputs enabled with cso for detailed descriptions for the wetting current auto-scaling, refer to section wetting current auto-scaling . 20-18 wc_in23 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 17-15 wc_in22 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 14-12 wc_in20_in21 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current
82 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 38. wc_cfg1 register field descriptions (continued) bit field type reset description 11-9 wc_in18_in19 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 8-6 wc_in16_in17 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 5-3 wc_in14_in15 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current 2-0 wc_in12_in13 r/w 0h 0h = no wetting current 1h = 1ma (typ.) wetting current 2h = 2ma (typ.) wetting current 3h = 5ma (typ.) wetting current 4h = 10ma (typ.) wetting current 5h-7h = 15ma (typ.) wetting current
83 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.28 ccp_cfg0 register (offset = 1fh) [reset = 0h] ccp_cfg0 is shown in figure 65 and described in table 39 . return to summary table . figure 65. ccp_cfg0 register 23 22 21 20 19 18 17 16 15 14 13 12 reserved r-0h 11 10 9 8 7 6 5 4 3 2 1 0 reserved ccp_time wc_ccp 3 wc_ccp 2 wc_ccp 1 wc_ccp 0 r-0h r-0h r-0h r-0h r-0h r-0h legend: r/w = read/write; r = read only table 39. ccp_cfg0 register field descriptions bit field type reset description 23-7 reserved r 0h reserved 6-4 ccp_time r/w 0h wetting current activation time in ccp mode 0h = 64 s 1h = 128 s 2h = 192 s 3h = 256 s 4h = 320 s 5h = 384 s 6h = 448 s 7h = 512 s 3 wc_ccp3 r/w 0h wetting current setting for in18 to in23 in ccp mode 0h = 10ma (typ.) wetting current 1h = 15ma (typ.) wetting current 2 wc_ccp2 r/w 0h wetting current setting for in12 to in17 in ccp mode 0h = 10ma (typ.) wetting current 1h = 15ma (typ.) wetting current 1 wc_ccp1 r/w 0h wetting current setting for in6 to in11 in ccp mode 0h = 10ma (typ.) wetting current 1h = 15ma (typ.) wetting current 0 wc_ccp0 r/w 0h wetting current setting for in0 to in5 in ccp mode 0h = 10ma (typ.) wetting current 1h = 15ma (typ.) wetting current
84 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.29 ccp_cfg1 register (offset = 20h) [reset = 0h] ccp_cfg1 is shown in figure 66 and described in table 40 . return to summary table . figure 66. ccp_cfg1 register 23 22 21 20 19 18 17 16 ccp_in23 ccp_in22 ccp_in21 ccp_in20 ccp_in19 ccp_in18 ccp_in17 ccp_in16 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 15 14 13 12 11 10 9 8 ccp_in15 ccp_in14 ccp_in13 ccp_in12 ccp_in11 ccp_in10 ccp_in9 ccp_in8 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 7 6 5 4 3 2 1 0 ccp_in7 ccp_in6 ccp_in5 ccp_in4 ccp_in3 ccp_in2 ccp_in1 ccp_in0 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 40. ccp_cfg1 register field descriptions bit field type reset description 23 ccp_in23 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 22 ccp_in22 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 21 ccp_in21 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 20 ccp_in20 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 19 ccp_in19 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 18 ccp_in18 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 17 ccp_in17 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 16 ccp_in16 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 15 ccp_in15 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 14 ccp_in14 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 13 ccp_in13 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 12 ccp_in12 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 11 ccp_in11 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 10 ccp_in10 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated
85 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 40. ccp_cfg1 register field descriptions (continued) bit field type reset description 9 ccp_in9 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 8 ccp_in8 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 7 ccp_in7 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 6 ccp_in6 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 5 ccp_in5 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 4 ccp_in4 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 3 ccp_in3 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 2 ccp_in2 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 1 ccp_in1 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated 0 ccp_in0 r/w 0h 0h = no ccp wetting current 1h = ccp wetting current activated
86 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.30 thres_comp register (offset = 21h) [reset = 0h] thres_comp is shown in figure 67 and described in table 41 . return to summary table . figure 67. thres_comp register 23 22 21 20 19 18 17 16 reserved r-0h 15 14 13 12 11 10 9 8 reserved thres_comp_in20_in23 thres_comp_in16_in19 r-0h r/w-0h r/w-0h 7 6 5 4 3 2 1 0 thres_comp_in12_in15 thres_comp_in8_in11 thres_comp_in4_in7 thres_comp_in0_in3 r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only table 41. thres_comp register field descriptions bit field type reset description 31-12 reserved r 0h reserved 11-10 thres_comp_in20_in2 3 r/w 0h these 2 bits configures the comparator thresholds for input channels in20 to in23 0h = comparator threshold set to 2v 1h = comparator threshold set to 2.7v 2h = comparator threshold set to 3v 3h = comparator threshold set to 4v 9-8 thres_comp_in16_in1 9 r/w 0h these 2 bits configures the comparator thresholds for input channels in16 to in19 0h = comparator threshold set to 2v 1h = comparator threshold set to 2.7v 2h = comparator threshold set to 3v 3h = comparator threshold set to 4v 7-6 thres_comp_in12_in1 5 r/w 0h these 2 bits configures the comparator thresholds for input channels in12 to in15 0h = comparator threshold set to 2v 1h = comparator threshold set to 2.7v 2h = comparator threshold set to 3v 3h = comparator threshold set to 4v 5-4 thres_comp_in8_in11 r/w 0h these 2 bits configures the comparator thresholds for input channels in8 to in11 0h = comparator threshold set to 2v 1h = comparator threshold set to 2.7v 2h = comparator threshold set to 3v 3h = comparator threshold set to 4v 3-2 thres_comp_in4_in7 r/w 0h these 2 bits configures the comparator thresholds for input channels in4 to in7 0h = comparator threshold set to 2v 1h = comparator threshold set to 2.7v 2h = comparator threshold set to 3v 3h = comparator threshold set to 4v
87 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 41. thres_comp register field descriptions (continued) bit field type reset description 1-0 thres_comp_in0_in3 r/w 0h these 2 bits configures the comparator thresholds for input channels in0 to in3 0h = comparator threshold set to 2v 1h = comparator threshold set to 2.7v 2h = comparator threshold set to 3v 3h = comparator threshold set to 4v
88 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.31 int_en_comp1 register (offset = 22h) [reset = 0h] int_en_comp1 is shown in figure 68 and described in table 42 . return to summary table . figure 68. int_en_comp1 register 23 22 21 20 19 18 17 16 15 14 13 12 inc_en_11 inc_en_10 inc_en_9 inc_en_8 inc_en_7 inc_en_6 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 inc_en_5 inc_en_4 inc_en_3 inc_en_2 inc_en_1 inc_en_0 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 42. int_en_comp1 register field descriptions bit field type reset description 23-22 inc_en_11 r/w 0h 0h = no interrupt generation for in11 1h = interrupt generation on rising edge above thres_comp_in8_in11 for in11 2h = interrupt generation on falling edge below thres_comp_in8_in11 for in11 3h = interrupt generation on falling and rising edge of thres_comp_in8_in11 for in11 21-20 inc_en_10 r/w 0h 0h = no interrupt generation for in10 1h = interrupt generation on rising edge above thres_comp_in8_in11 for in10 2h = interrupt generation on falling edge below thres_comp_in8_in11 for in10 3h = interrupt generation on falling and rising edge of thres_comp_in8_in11 for in10 19-18 inc_en_9 r/w 0h 0h = no interrupt generation for in9 1h = interrupt generation on rising edge above thres_comp_in8_in11 for in9 2h = interrupt generation on falling edge below thres_comp_in8_in11 for in9 3h = interrupt generation on falling and rising edge of thres_comp_in8_in11 for in9 17-16 inc_en_8 r/w 0h 0h = no interrupt generation for in8 1h = interrupt generation on rising edge above thres_comp_in8_in11 for in8 2h = interrupt generation on falling edge below thres_comp_in8_in11 for in8 3h = interrupt generation on falling and rising edge of thres_comp_in8_in11 for in8 15-14 inc_en_7 r/w 0h 0h = no interrupt generation for in7 1h = interrupt generation on rising edge above thres_comp_in4_in7 for in7 2h = interrupt generation on falling edge below thres_comp_in4_in7 for in7 3h = interrupt generation on falling and rising edge of thres_comp_in4_in7 for in7
89 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 42. int_en_comp1 register field descriptions (continued) bit field type reset description 13-12 inc_en_6 r/w 0h 0h = no interrupt generation for in6 1h = interrupt generation on rising edge above thres_comp_in4_in7 for in6 2h = interrupt generation on falling edge below thres_comp_in4_in7 for in6 3h = interrupt generation on falling and rising edge of thres_comp_in4_in7 for in6 11-10 inc_en_5 r/w 0h 0h = no interrupt generation for in5 1h = interrupt generation on rising edge above thres_comp_in4_in7 for in5 2h = interrupt generation on falling edge below thres_comp_in4_in7 for in5 3h = interrupt generation on falling and rising edge of thres_comp_in4_in7 for in5 9-8 inc_en_4 r/w 0h 0h = no interrupt generation for in4 1h = interrupt generation on rising edge above thres_comp_in4_in7 for in4 2h = interrupt generation on falling edge below thres_comp_in4_in7 for in4 3h = interrupt generation on falling and rising edge of thres_comp_in4_in7 for in4 7-6 inc_en_3 r/w 0h 0h = no interrupt generation for in3 1h = interrupt generation on rising edge above thres_comp_in0_in3 for in3 2h = interrupt generation on falling edge below thres_comp_in0_in3 for in3 3h = interrupt generation on falling and rising edge of thres_comp_in0_in3 for in3 5-4 inc_en_2 r/w 0h 0h = no interrupt generation for in2 1h = interrupt generation on rising edge above thres_comp_in0_in3 for in2 2h = interrupt generation on falling edge below thres_comp_in0_in3 for in2 3h = interrupt generation on falling and rising edge of thres_comp_in0_in3 for in2 3-2 inc_en_1 r/w 0h 0h = no interrupt generation for in1 1h = interrupt generation on rising edge above thres_comp_in0_in3 for in1 2h = interrupt generation on falling edge below thres_comp_in0_in3 for in1 3h = interrupt generation on falling and rising edge of thres_comp_in0_in3 for in1 1-0 inc_en_0 r/w 0h 0h = no interrupt generation for in0 1h = interrupt generation on rising edge above thres_comp_in0_in3 for in0 2h = interrupt generation on falling edge below thres_comp_in0_in3 for in0 3h = interrupt generation on falling and rising edge of thres_comp_in0_in3 for in0
90 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.32 int_en_comp2 register (offset = 23h) [reset = 0h] int_en_comp2 is shown in figure 69 and described in table 43 . return to summary table . figure 69. int_en_comp2 register 23 22 21 20 19 18 17 16 15 14 13 12 inc_en_23 inc_en_22 inc_en_21 inc_en_20 inc_en_19 inc_en_18 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 inc_en_17 inc_en_16 inc_en_15 inc_en_14 inc_en_13 inc_en_12 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 43. int_en_comp2 register field descriptions bit field type reset description 23-22 inc_en_23 r/w 0h 0h = no interrupt generation for in23 1h = interrupt generation on rising edge above thres_comp_in20_in23 for in23 2h = interrupt generation on falling edge below thres_comp_in20_in23 for in23 3h = interrupt generation on falling and rising edge of thres_comp_in20_in23 for in23 21-20 inc_en_22 r/w 0h 0h = no interrupt generation for in22 1h = interrupt generation on rising edge above thres_comp_in20_in23 for in22 2h = interrupt generation on falling edge below thres_comp_in20_in23 for in22 3h = interrupt generation on falling and rising edge of thres_comp_in20_in23 for in22 19-18 inc_en_21 r/w 0h 0h = no interrupt generation for in21 1h = interrupt generation on rising edge above thres_comp_in20_in23 for in21 2h = interrupt generation on falling edge below thres_comp_in20_in23 for in21 3h = interrupt generation on falling and rising edge of thres_comp_in20_in23 for in21 17-16 inc_en_20 r/w 0h 0h = no interrupt generation for in20 1h = interrupt generation on rising edge above thres_comp_in20_in23 for in20 2h = interrupt generation on falling edge below thres_comp_in20_in23 for in20 3h = interrupt generation on falling and rising edge of thres_comp_in20_in23 for in20 15-14 inc_en_19 r/w 0h 0h = no interrupt generation for in19 1h = interrupt generation on rising edge above thres_comp_in16_in19 for in19 2h = interrupt generation on falling edge below thres_comp_in16_in19 for in19 3h = interrupt generation on falling and rising edge of thres_comp_in16_in19 for in19
91 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 43. int_en_comp2 register field descriptions (continued) bit field type reset description 13-12 inc_en_18 r/w 0h 0h = no interrupt generation for in18 1h = interrupt generation on rising edge above thres_comp_in16_in19 for in18 2h = interrupt generation on falling edge below thres_comp_in16_in19 for in18 3h = interrupt generation on falling and rising edge of thres_comp_in16_in19 for in18 11-10 inc_en_17 r/w 0h 0h = no interrupt generation for in17 1h = interrupt generation on rising edge above thres_comp_in16_in19 for in17 2h = interrupt generation on falling edge below thres_comp_in16_in19 for in17 3h = interrupt generation on falling and rising edge of thres_comp_in16_in19 for in17 9-8 inc_en_16 r/w 0h 0h = no interrupt generation for in16 1h = interrupt generation on rising edge above thres_comp_in16_in19 for in16 2h = interrupt generation on falling edge below thres_comp_in16_in19 for in16 3h = interrupt generation on falling and rising edge of thres_comp_in16_in19 for in16 7-6 inc_en_15 r/w 0h 0h = no interrupt generation for in15 1h = interrupt generation on rising edge above thres_comp_in12_in15 for in15 2h = interrupt generation on falling edge below thres_comp_in12_in15 for in15 3h = interrupt generation on falling and rising edge of thres_comp_in12_in15 for in15 5-4 inc_en_14 r/w 0h 0h = no interrupt generation for in14 1h = interrupt generation on rising edge above thres_comp_in12_in15 for in14 2h = interrupt generation on falling edge below thres_comp_in12_in15 for in14 3h = interrupt generation on falling and rising edge of thres_comp_in12_in15 for in14 3-2 inc_en_13 r/w 0h 0h = no interrupt generation for in13 1h = interrupt generation on rising edge above thres_comp_in12_in15 for in13 2h = interrupt generation on falling edge below thres_comp_in12_in15 for in13 3h = interrupt generation on falling and rising edge of thres_comp_in12_in15 for in13 1-0 inc_en_12 r/w 0h 0h = no interrupt generation for in12 1h = interrupt generation on rising edge above thres_comp_in12_in15 for in12 2h = interrupt generation on falling edge below thres_comp_in12_in15 for in12 3h = interrupt generation on falling and rising edge of thres_comp_in12_in15 for in12
92 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.33 int_en_cfg0 register (offset = 24h) [reset = 0h] int_en_cfg0 is shown in figure 70 and described in table 44 . return to summary table . figure 70. int_en_cfg0 register 23 22 21 20 19 18 17 16 reserved r-0h 15 14 13 12 11 10 9 8 reserved adc_diag_en wet_diag_e n vs1_en vs0_en r-0h r/w-0h r/w-0h r/w-0h r/w-0h 7 6 5 4 3 2 1 0 crc_calc_e n uv_en ov_en tw_en tsd_en ssc_en prty_fail_e n spi_fail_en r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only table 44. int_en_cfg0 register field descriptions bit field type reset description 23-12 reserved r 0h reserved 11 adc_diag_en r/w 0h 0h = int pin assertion due to adc error disabled. 1h = int pin assertion due to adc error enabled. 10 wet_diag_en r/w 0h 0h = int pin assertion due to wetting current error disabled. 1h = int pin assertion due to wetting current error enabled. 9 vs1_en r/w 0h 0h = int pin assertion due to vs1 threshold crossing disabled. 1h = int pin assertion due to vs1 threshold crossing enabled. 8 vs0_en r/w 0h 0h = int pin assertion due to vs0 threshold crossing disabled. 1h = int pin assertion due to vs0 threshold crossing enabled. 7 crc_calc_en r/w 0h 0h = int pin assertion due to crc calculation completion disabled. 1h = int pin assertion due to crc calculation completion enabled. 6 uv_en r/w 0h 0h = int pin assertion due to uv event disabled. 1h = int pin assertion due to uv event enabled. 5 ov_en r/w 0h 0h = int pin assertion due to ov event disabled. 1h = int pin assertion due to ov event enabled. 4 tw_en r/w 0h 0h = int pin assertion due to tw event disabled. 1h = int pin assertion due to tw event enabled. 3 tsd_en r/w 0h 0h = int pin assertion due to tsd event disabled. 1h = int pin assertion due to tsd event enabled. 2 ssc_en r/w 0h 0h = int pin assertion due to ssc event disabled. 1h = int pin assertion due to ssc event enabled. 1 prty_fail_en r/w 0h 0h = int pin assertion due to parity fail event disabled. 1h = int pin assertion due to parity fail event enabled. 0 spi_fail_en r/w 0h 0h = int pin assertion due to spi fail event disabled. 1h = int pin assertion due to spi fail event enabled.
93 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.34 int_en_cfg1 register (offset = 25h) [reset = 0h] int_en_cfg1 is shown in figure 71 and described in table 45 . return to summary table . figure 71. int_en_cfg1 register 23 22 21 20 19 18 17 16 15 14 13 12 in11_en in10_en in9_en in8_en in7_en in6_en r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 in5_en in4_en in3_en in2_en in1_en in0_en r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 45. int_en_cfg1 register field descriptions bit field type reset description 23-22 in11_en r/w 0h 0h = no interrupt generation for in11 1h = interrupt generation on rising edge above thresx for in11 2h = interrupt generation on falling edge below thresx for in11 3h = interrupt generation on falling and rising edge of thresx for in11 21-20 in10_en r/w 0h 0h = no interrupt generation for in10 1h = interrupt generation on rising edge above thresx for in10 2h = interrupt generation on falling edge below thresx for in10 3h = interrupt generation on falling and rising edge of thresx for in10 19-18 in9_en r/w 0h 0h = no interrupt generation for in9 1h = interrupt generation on rising edge above thresx for in9 2h = interrupt generation on falling edge below thresx for in9 3h = interrupt generation on falling and rising edge of thresx for in9 17-16 in8_en r/w 0h 0h = no interrupt generation for in8 1h = interrupt generation on rising edge above thresx for in8 2h = interrupt generation on falling edge below thresx for in8 3h = interrupt generation on falling and rising edge of thresx for in8 15-14 in7_en r/w 0h 0h = no interrupt generation for in7 1h = interrupt generation on rising edge above thresx for in7 2h = interrupt generation on falling edge below thresx for in7 3h = interrupt generation on falling and rising edge of thresx for in7 13-12 in6_en r/w 0h 0h = no interrupt generation for in6 1h = interrupt generation on rising edge above thresx for in6 2h = interrupt generation on falling edge below thresx for in6 3h = interrupt generation on falling and rising edge of thresx for in6 11-10 in5_en r/w 0h 0h = no interrupt generation for in5 1h = interrupt generation on rising edge above thresx for in5 2h = interrupt generation on falling edge below thresx for in5 3h = interrupt generation on falling and rising edge of thresx for in5
94 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 45. int_en_cfg1 register field descriptions (continued) bit field type reset description 9-8 in4_en r/w 0h 0h = no interrupt generation for in4 1h = interrupt generation on rising edge above thresx for in4 2h = interrupt generation on falling edge below thresx for in4 3h = interrupt generation on falling and rising edge of thresx for in4 7-6 in3_en r/w 0h 0h = no interrupt generation for in3 1h = interrupt generation on rising edge above thresx for in3 2h = interrupt generation on falling edge below thresx for in3 3h = interrupt generation on falling and rising edge of thresx for in3 5-4 in2_en r/w 0h 0h = no interrupt generation for in2 1h = interrupt generation on rising edge above thresx for in2 2h = interrupt generation on falling edge below thresx for in2 3h = interrupt generation on falling and rising edge of thresx for in2 3-2 in1_en r/w 0h 0h = no interrupt generation for in1 1h = interrupt generation on rising edge above thresx for in1 2h = interrupt generation on falling edge below thresx for in1 3h = interrupt generation on falling and rising edge of thresx for in1 1-0 in0_en r/w 0h 0h = no interrupt generation for in0 1h = interrupt generation on rising edge above thresx for in0 2h = interrupt generation on falling edge below thresx for in0 3h = interrupt generation on falling and rising edge of thresx for in0
95 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.35 int_en_cfg2 register (offset = 26h) [reset = 0h] int_en_cfg2 is shown in figure 72 and described in table 46 . return to summary table . figure 72. int_en_cfg2 register 23 22 21 20 19 18 17 16 15 14 13 12 in17_en in16_en in15_en r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 in14_en in13_en in12_en r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 46. int_en_cfg2 register field descriptions bit field type reset description 23-20 in17_en r/w 0h xx00: no interrupt generation for in17 w.r.t. thres2a xx01: interrupt generation on rising edge above thres2a for in17 xx10: interrupt generation on falling edge below thres2a for in17 xx11: interrupt generation on falling and rising edge of thres2a for in17 00xx: no interrupt generation for in17 w.r.t. thres2b 01xx: interrupt generation on rising edge above thres2b for in17 10xx: interrupt generation on falling edge below thres2b for in17 11xx: interrupt generation on falling and rising edge of thres2b for in17 19-16 in16_en r/w 0h xx00: no interrupt generation for in16 w.r.t. thres2a xx01: interrupt generation on rising edge above thres2a for in16 xx10: interrupt generation on falling edge below thres2a for in16 xx11: interrupt generation on falling and rising edge of thres2a for in16 00xx: no interrupt generation for in16 w.r.t. thres2b 01xx: interrupt generation on rising edge above thres2b for in16 10xx: interrupt generation on falling edge below thres2b for in16 11xx: interrupt generation on falling and rising edge of thres2b for in16 15-12 in15_en r/w 0h xx00: no interrupt generation for in15 w.r.t. thres2a xx01: interrupt generation on rising edge above thres2a for in15 xx10: interrupt generation on falling edge below thres2a for in15 xx11: interrupt generation on falling and rising edge of thres2a for in15 00xx: no interrupt generation for in15 w.r.t. thres2b 01xx: interrupt generation on rising edge above thres2b for in15 10xx: interrupt generation on falling edge below thres2b for in15 11xx: interrupt generation on falling and rising edge of thres2b for in15
96 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 46. int_en_cfg2 register field descriptions (continued) bit field type reset description 11-8 in14_en r/w 0h xx00: no interrupt generation for in14 w.r.t. thres2a xx01: interrupt generation on rising edge above thres2a for in14 xx10: interrupt generation on falling edge below thres2a for in14 xx11: interrupt generation on falling and rising edge of thres2a for in14 00xx: no interrupt generation for in14 w.r.t. thres2b 01xx: interrupt generation on rising edge above thres2b for in14 10xx: interrupt generation on falling edge below thres2b for in14 11xx: interrupt generation on falling and rising edge of thres2b for in14 7-4 in13_en r/w 0h xx00: no interrupt generation for in13 w.r.t. thres2a xx01: interrupt generation on rising edge above thres2a for in13 xx10: interrupt generation on falling edge below thres2a for in13 xx11: interrupt generation on falling and rising edge of thres2a for in13 00xx: no interrupt generation for in13 w.r.t. thres2b 01xx: interrupt generation on rising edge above thres2b for in13 10xx: interrupt generation on falling edge below thres2b for in13 11xx: interrupt generation on falling and rising edge of thres2b for in13 3-0 in12_en r/w 0h xx00: no interrupt generation for in12 w.r.t. thres2a xx01: interrupt generation on rising edge above thres2a for in12 xx10: interrupt generation on falling edge below thres2a for in12 xx11: interrupt generation on falling and rising edge of thres2a for in12 00xx: no interrupt generation for in12 w.r.t. thres2b 01xx: interrupt generation on rising edge above thres2b for in12 10xx: interrupt generation on falling edge below thres2b for in12 11xx: interrupt generation on falling and rising edge of thres2b for in12
97 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.36 int_en_cfg3 register (offset = 27h) [reset = 0h] int_en_cfg3 is shown in figure 73 and described in table 47 . return to summary table . figure 73. int_en_cfg3 register 23 22 21 20 19 18 17 16 15 14 13 12 in21_en in20_en r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 in19_en in18_en r/w-0h r/w-0h legend: r/w = read/write table 47. int_en_cfg3 register field descriptions bit field type reset description 23-18 in21_en r/w 0h xxxx00: no interrupt generation for in21 w.r.t. thres3a xxxx01: interrupt generation on rising edge above thres3a for in21 xxxx10: interrupt generation on falling edge below thres3a for in21 xxxx11: interrupt generation on falling and rising edge of thres3a for in21 xx00xx: no interrupt generation for in21 w.r.t. thres3b xx01xx: interrupt generation on rising edge above thres3b for in21 xx10xx: interrupt generation on falling edge below thres3b for in21 xx11xx: interrupt generation on falling and rising edge of thres3b for in21 00xxxx: no interrupt generation for in21 w.r.t. thres3c 01xxxx: interrupt generation on rising edge above thres3c for in21 10xxxx: interrupt generation on falling edge below thres3c for in21 11xxxx: interrupt generation on falling and rising edge of thres3c for in21 17-12 in20_en r/w 0h xxxx00: no interrupt generation for in20 w.r.t. thres3a xxxx01: interrupt generation on rising edge above thres3a for in20 xxxx10: interrupt generation on falling edge below thres3a for in20 xxxx11: interrupt generation on falling and rising edge of thres3a for in20 xx00xx: no interrupt generation for in20 w.r.t. thres3b xx01xx: interrupt generation on rising edge above thres3b for in20 xx10xx: interrupt generation on falling edge below thres3b for in20 xx11xx: interrupt generation on falling and rising edge of thres3b for in20 00xxxx: no interrupt generation for in20 w.r.t. thres3c 01xxxx: interrupt generation on rising edge above thres3c for in20 10xxxx: interrupt generation on falling edge below thres3c for in20 11xxxx: interrupt generation on falling and rising edge of thres3c for in20
98 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 47. int_en_cfg3 register field descriptions (continued) bit field type reset description 11-6 in19_en r/w 0h xxxx00: no interrupt generation for in19 w.r.t. thres3a xxxx01: interrupt generation on rising edge above thres3a for in19 xxxx10: interrupt generation on falling edge below thres3a for in19 xxxx11: interrupt generation on falling and rising edge of thres3a for in19 xx00xx: no interrupt generation for in19 w.r.t. thres3b xx01xx: interrupt generation on rising edge above thres3b for in19 xx10xx: interrupt generation on falling edge below thres3b for in19 xx11xx: interrupt generation on falling and rising edge of thres3b for in19 00xxxx: no interrupt generation for in19 w.r.t. thres3c 01xxxx: interrupt generation on rising edge above thres3c for in19 10xxxx: interrupt generation on falling edge below thres3c for in19 11xxxx: interrupt generation on falling and rising edge of thres3c for in19 5-0 in18_en r/w 0h xxxx00: no interrupt generation for in18 w.r.t. thres3a xxxx01: interrupt generation on rising edge above thres3a for in18 xxxx10: interrupt generation on falling edge below thres3a for in18 xxxx11: interrupt generation on falling and rising edge of thres3a for in18 xx00xx: no interrupt generation for in18 w.r.t. thres3b xx01xx: interrupt generation on rising edge above thres3b for in18 xx10xx: interrupt generation on falling edge below thres3b for in18 xx11xx: interrupt generation on falling and rising edge of thres3b for in18 00xxxx: no interrupt generation for in18 w.r.t. thres3c 01xxxx: interrupt generation on rising edge above thres3c for in18 10xxxx: interrupt generation on falling edge below thres3c for in18 11xxxx: interrupt generation on falling and rising edge of thres3c for in18
99 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.37 int_en_cfg4 register (offset = 28h) [reset = 0h] int_en_cfg4 is shown in figure 74 and described in table 48 . return to summary table . figure 74. int_en_cfg4 register 23 22 21 20 19 18 17 16 15 14 13 12 vs_th1_en vs_th0_en in23_en r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 in23_en in22_en r/w-0h r/w-0h legend: r/w = read/write table 48. int_en_cfg4 register field descriptions bit field type reset description 23-20 vs_th1_en r/w 0h xx00: no interrupt generation for v s w.r.t. vs1_thres2a xx01: interrupt generation on rising edge above vs1_thres2a for v s xx10: interrupt generation on falling edge below vs1_thres2a for v s xx11: interrupt generation on falling and rising edge of vs1_thres2a for v s 00xx: no interrupt generation for v s w.r.t. vs1_thres2b 01xx: interrupt generation on rising edge above vs1_thres2b for v s 10xx: interrupt generation on falling edge below vs1_thres2b for v s 11xx: interrupt generation on falling and rising edge of vs1_thres2b for v s 19-16 vs_th0_en r/w 0h xx00: no interrupt generation for v s w.r.t. vs0_thres2a xx01: interrupt generation on rising edge above vs0_thres2a for v s xx10: interrupt generation on falling edge below vs0_thres2a for v s xx11: interrupt generation on falling and rising edge of vs0_thres2a for vs 00xx: no interrupt generation for v s w.r.t. vs0_thres2b 01xx: interrupt generation on rising edge above vs0_thres2b for v s 10xx: interrupt generation on falling edge below vs0_thres2b for v s 11xx: interrupt generation on falling and rising edge of vs0_thres2b for v s
100 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 48. int_en_cfg4 register field descriptions (continued) bit field type reset description 15-6 in23_en r/w 0h xxxxxxxx00: no interrupt generation for in23 w.r.t. thres3a xxxxxxxx01: interrupt generation on rising edge above thres3a for in23 xxxxxxxx10: interrupt generation on falling edge below thres3a for in23 xxxxxxxx11: interrupt generation on falling and rising edge of thres3a for in23 xxxxxx00xx: no interrupt generation for in23 w.r.t. thres3b xxxxxx01xx: interrupt generation on rising edge above thres3b for in23 xxxxxx10xx: interrupt generation on falling edge below thres3b for in23 xxxxxx11xx: interrupt generation on falling and rising edge of thres3b for in23 xxxx00xxxx: no interrupt generation for in23 w.r.t. thres3c xxxx01xxxx: interrupt generation on rising edge above thres3c for in23 xxxx10xxxx: interrupt generation on falling edge below thres3c for in23 xxxx11xxxx: interrupt generation on falling and rising edge of thres3c for in23 xx00xxxxxx: no interrupt generation for in23 w.r.t. thres8 xx01xxxxxx: interrupt generation on rising edge above thres8 for in23 xx10xxxxxx: interrupt generation on falling edge below thres8 for in23 xx11xxxxxx: interrupt generation on falling and rising edge of thres8 for in23 00xxxxxxxx: no interrupt generation for in23 w.r.t. thres9 01xxxxxxxx: interrupt generation on rising edge above thres9 for in23 10xxxxxxxx: interrupt generation on falling edge below thres9 for in23 11xxxxxxxx: interrupt generation on falling and rising edge of thres9 for in23 5-0 in22_en r/w 0h xxxx00: no interrupt generation for in22 w.r.t. thres3a xxxx01: interrupt generation on rising edge above thres3a for in22 xxxx10: interrupt generation on falling edge below thres3a for in22 xxxx11: interrupt generation on falling and rising edge of thres3a for in22 xx00xx: no interrupt generation for in22 w.r.t. thres3b xx01xx: interrupt generation on rising edge above thres3b for in22 xx10xx: interrupt generation on falling edge below thres3b for in22 xx11xx: interrupt generation on falling and rising edge of thres3b for in22 00xxxx: no interrupt generation for in22 w.r.t. thres3c 01xxxx: interrupt generation on rising edge above thres3c for in22 10xxxx: interrupt generation on falling edge below thres3c for in22 11xxxx: interrupt generation on falling and rising edge of thres3c for in22
101 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.38 thres_cfg0 register (offset = 29h) [reset = 0h] thres_cfg0 is shown in figure 75 and described in table 49 . return to summary table . figure 75. thres_cfg0 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved thres1 thres0 r-0h r-0h r-0h legend: r/w = read/write; r = read only table 49. thres_cfg0 register field descriptions bit field type reset description 31-20 reserved r 0h reserved 19-10 thres1 r/w 0h 10-bits value of threshold 1: bit10: lsb bit19: msb 9-0 thres0 r/w 0h 10-bits value of threshold 0 bit0: lsb bit9: msb 8.6.39 thres_cfg1 register (offset = 2ah) [reset = 0h] thres_cfg1 is shown in figure 76 and described in table 50 . return to summary table . figure 76. thres_cfg1 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved thres3 thres2 r-0h r-0h r-0h legend: r/w = read/write; r = read only table 50. thres_cfg1 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 thres3 r/w 0h 10-bits value of threshold 3: bit10: lsb bit19: msb 9-0 thres2 r/w 0h 10-bits value of threshold 2 bit0: lsb bit9: msb
102 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.40 thres_cfg2 register (offset = 2bh) [reset = 0h] thres_cfg2 is shown in figure 77 and described in table 51 . return to summary table . figure 77. thres_cfg2 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved thres5 thres4 r-0h r-0h r-0h legend: r/w = read/write; r = read only table 51. thres_cfg2 register field descriptions bit field type reset description 23-20 reserved r 0h reserved 19-10 thres5 r/w 0h 10-bits value of threshold 5: bit10: lsb bit19: msb 10-1 thres4 r/w 0h 10-bits value of threshold 4: bit0: lsb bit9: msb 8.6.41 thres_cfg3 register (offset = 2ch) [reset = x] thres_cfg3 is shown in figure 78 and described in table 52 . return to summary table . figure 78. thres_cfg3 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved thres6 thres7 r-0h r-0h r-0h legend: r/w = read/write; r = read only table 52. thres_cfg3 register field descriptions bit field type reset description 31-20 reserved r 0h reserved 19-10 thres7 r/w 0h 10-bits value of threshold 7: bit10: lsb bit19: msb 9-0 thres6 r/w 0h 10-bits value of threshold 6: bit0: lsb bit9: msb
103 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.42 thres_cfg4 register (offset = 2dh) [reset = x] thres_cfg4 is shown in figure 79 and described in table 53 . return to summary table . figure 79. thres_cfg4 register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved thres9 thres8 r-0h r-0h r-0h legend: r/w = read/write; r = read only table 53. thres_cfg4 register field descriptions bit field type reset description 31-20 reserved r 0h reserved 19-10 thres9 r/w 0h 10-bits value of threshold 9: bit10: lsb bit19: msb 9-0 thres8 r/w 0h 10-bits value of threshold 8: bit0: lsb bit9: msb
104 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.43 thresmap_cfg0 register (offset = 2eh) [reset = 0h] thresmap_cfg0 is shown in figure 80 and described in table 54 . return to summary table . figure 80. thresmap_cfg0 register 23 22 21 20 19 18 17 16 15 14 13 12 thresmap_in7 thresmap_in6 thresmap_in5 thresmap_in4 r/w-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 thresmap_in3 thresmap_in2 thresmap_in1 thresmap_in0 r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 54. thresmap_cfg0 register field descriptions bit field type reset description 23-21 thresmap_in7 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 20-18 thresmap_in6 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 17-15 thresmap_in5 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 14-12 thresmap_in4 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7
105 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 54. thresmap_cfg0 register field descriptions (continued) bit field type reset description 11-9 thresmap_in3 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 8-6 thresmap_in2 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 5-3 thresmap_in1 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 2-0 thresmap_in0 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7
106 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.44 thresmap_cfg1 register (offset = 2fh) [reset = 0h] thresmap_cfg1 is shown in figure 81 and described in table 55 . return to summary table . figure 81. thresmap_cfg1 register 23 22 21 20 19 18 17 16 15 14 13 12 reserved thresmap_in12_in17_thres 2b thresmap_in12_in17_thres 2a r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 thresmap_in11 thresmap_in10 thresmap_in9 thresmap_in8 r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only table 55. thresmap_cfg1 register field descriptions bit field type reset description 23-18 reserved r 0h reserved 17-15 thresmap_in12_in17_ thres2b r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 14-12 thresmap_in12_in17_ thres2a r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 11-9 thresmap_in11 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 8-6 thresmap_in10 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7
107 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 55. thresmap_cfg1 register field descriptions (continued) bit field type reset description 5-3 thresmap_in9 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 2-0 thresmap_in8 r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7
108 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.45 thresmap_cfg2 register (offset = 30h) [reset = 0h] thresmap_cfg2 is shown in figure 82 and described in table 56 . return to summary table . figure 82. thresmap_cfg2 register 23 22 21 20 19 18 17 16 15 14 13 12 reserved thresmap_vs1_thres2b thresmap_vs1_thres2a thresmap_vs0_thres2b r-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 thresmap_vs0_thres2a thresmap_in18_in23_thres 3c thresmap_in18_in23_thres 3b thresmap_in18_in23_thres 3a r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only table 56. thresmap_cfg2 register field descriptions bit field type reset description 23-21 reserved r 0h reserved 20-18 thresmap_vs1_thre s2b r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 17-15 thresmap_vs1_thre s2a r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 14-12 thresmap_vs0_thre s2b r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 11-9 thresmap_vs0_thre s2a r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7
109 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 56. thresmap_cfg2 register field descriptions (continued) bit field type reset description 8-6 thresmap_in18_in23_ thres3c r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 5-3 thresmap_in18_in23_ thres3b r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7 2-0 thresmap_in18_in23_ thres3a r/w 0h 0h = thres0 1h = thres1 2h = thres2 3h = thres3 4h = thres4 5h = thres5 6h = thres6 7h = thres7
110 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.46 matrix register (offset = 31h) [reset = 0h] matrix is shown in figure 83 and described in table 57 . return to summary table . figure 83. matrix register 23 22 21 20 19 18 17 16 15 14 13 12 reserved in_com_en thres_com r-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 thres_com matrix poll_act_time_m r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only table 57. matrix register field descriptions bit field type reset description 23-17 reserved r 0h reserved 16-15 in_com_en r/w 0h 0h = no interrupt generation for w.r.t. threshold thres_com 1h = interrupt generation on rising edge above threshold thres_com 2h = interrupt generation on falling edge below threshold thres_com 3h = interrupt generation on falling and rising edge of threshold thres_com 14-5 thres_com r/w 0h 10-bits value of threshold thres_com: bit5: lsb bit14: msb 4-3 matrix r/w 0h 0h = no matrix, regular inputs only 1h = 4x4 matrix 2h = 5x5 matrix 3h = 6x6 matrix 2-0 poll_act_time_m r/w 0h polling active time setting for the matrix inputs: 0h = 64 s 1h = 128 s 2h = 256 s 3h = 384 s 4h = 512 s 5h = 768 s 6h = 1024 s 7h = 1360 s
111 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.6.47 mode register (offset = 32h) [reset = 0h] mode is shown in figure 84 and described in table 58 . return to summary table . figure 84. mode register 23 22 21 20 19 18 17 16 15 14 13 12 m_in23 m_in22 m_in21 m_in20 m_in19 m_in18 m_in17 m_in16 m_in15 m_in14 m_in13 m_in12 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h 11 10 9 8 7 6 5 4 3 2 1 0 m_in11 m_in10 m_in9 m_in8 m_in7 m_in6 m_in5 m_in4 m_in3 m_in2 m_in1 m_in0 r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write table 58. mode register field descriptions bit field type reset description 23 m_in23 r/w 0h 0h = comparator mode for in23 1h = adc mode for in23 22 m_in22 r/w 0h 0h = comparator mode for in22 1h = adc mode for in22 21 m_in21 r/w 0h 0h = comparator mode for in21 1h = adc mode for in21 20 m_in20 r/w 0h 0h = comparator mode for in20 1h = adc mode for in20 19 m_in19 r/w 0h 0h = comparator mode for in19 1h = adc mode for in19 18 m_in18 r/w 0h 0h = comparator mode for in18 1h = adc mode for in18 17 m_in17 r/w 0h 0h = comparator mode for in17 1h = adc mode for in17 16 m_in16 r/w 0h 0h = comparator mode for in16 1h = adc mode for in16 15 m_in15 r/w 0h 0h = comparator mode for in15 1h = adc mode for in15 14 m_in14 r/w 0h 0h = comparator mode for in14 1h = adc mode for in14 13 m_in13 r/w 0h 0h = comparator mode for in13 1h = adc mode for in13 12 m_in12 r/w 0h 0h = comparator mode for in12 1h = adc mode for in12 11 m_in11 r/w 0h 0h = comparator mode for in11 1h = adc mode for in11 10 m_in10 r/w 0h 0h = comparator mode for in10 1h = adc mode for in10 9 m_in9 r/w 0h 0h = comparator mode for in9 1h = adc mode for in9 8 m_in8 r/w 0h 0h = comparator mode for in8 1h = adc mode for in8
112 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 58. mode register field descriptions (continued) bit field type reset description 7 m_in7 r/w 0h 0h = comparator mode for in7 1h = adc mode for in7 6 m_in6 r/w 0h 0h = comparator mode for in6 1h = adc mode for in6 5 m_in5 r/w 0h 0h = comparator mode for in5 1h = adc mode for in5 4 m_in4 r/w 0h 0h = comparator mode for in4 1h = adc mode for in4 3 m_in3 r/w 0h 0h = comparator mode for in3 1h = adc mode for in1 2 m_in2 r/w 0h 0h = comparator mode for in2 1h = adc mode for in0 1 m_in1 r/w 0h 0h = comparator mode for in1 1h = adc mode for in1 0 m_in0 r/w 0h 0h = comparator mode for in0 1h = adc mode for in0 8.7 programming guidelines when configuring the TIC12400-Q1, it is critical to follow the programming guideline summarized below (see table 59 ) to ensure proper behavior of the device: table 59. TIC12400-Q1 programming guidelines category programming requirement threshold setup: ? continuous mode ? regular polling mode ? matrix mode (non-matrix inputs) ? thres2b thres2a (for in12 to in17) ? thres3c thres3b thres3a (for in18 to in22) ? thres9 thres8 thres3c thres3b thres3a (for in23) threshold setup: ? v s measurement ? vs0_thres2b vs0_thres2a ? vs1_thres2b vs1_thres2a 4x4 matrix mode (matrix [4:3] = 2'b01) ? poll_en=1 ? in_en[7:4]=4 ? b1111; in_en[13:10]= 4 ? b1111 ? mode[7:4] = 4 ? b0000; mode[13:10] = 4 ? b0000 ? cs_select[7:4]= 4 ? b1111; cs_select[13:10]= 4 ? b0000 ? iwett(csi) > iwett (cso): 1. wc_cfg0[20:18] > wc_cfg0[8:6] 2. wc_cfg0[23:21] > wc_cfg0[11:9] 3. wc_cfg1[2:0] > wc_cfg0[14:12] ? if tw event is expected, cso can only be set to 1ma or 2ma: 1. if wc_cfg0[8:6]= 3 ? b001: wc_cfg0[20:18]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg0[8:6]= 3 ? b010: wc_cfg0[20:18] = 3 ? b011 2. if wc_cfg0[11:9]= 3 ? b001: wc_cfg0[23:21]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg0[11:9]= 3 ? b010: wc_cfg0[23:21] = 3 ? b011 3. if wc_cfg1[2:0]= 3 ? b001: wc_cfg0[14:12]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg1[2:0]= 3 ? b010: wc_cfg0[14:12] = 3 ? b011
113 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated programming guidelines (continued) table 59. TIC12400-Q1 programming guidelines (continued) category programming requirement (1) this is a soft requirement to take advantage of the clean current polling feature. the feature takes no effect otherwise. (2) these are soft requirements to take advantage of the wetting current auto-scaling feature. the feature takes no effect otherwise. (3) if wcd is enabled, add additional 96 s (4) if ccp is enabled, add tccp_tran +tccp_time, where tccp_time is the timing setting configured in ccp_cfg0[6:4] 5x5 matrix mode (matrix [4:3] = 2'b10) ? poll_en=1 ? in_en[8:4]= 5 ? b11111; in_en[14:10]= 5 ? b11111 ? mode[8:4] = 5 ? b00000; mode[14:10] = 5 ? b00000 ? cs_select[8:4]= 5 ? b11111; cs_select[14:10]= 5 ? b00000 ? iwett(csi) > iwett (cso): 1. wc_cfg0[20:18] > wc_cfg0[8:6] 2. wc_cfg0[23:21] > wc_cfg0[11:9] 3. wc_cfg1[2:0] > wc_cfg0[14:12] 4. wc_cfg1[5:3] > wc_cfg0[17:15] ? if tw event is expected, cso can only be set to 1ma or 2ma: 1. if wc_cfg0[8:6]= 3 ? b001: wc_cfg0[20:18]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg0[8:6]= 3 ? b010: wc_cfg0[20:18] = 3 ? b011 2. if wc_cfg0[11:9]= 3 ? b001: wc_cfg0[23:21]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg0[11:9]= 3 ? b010: wc_cfg0[23:21] = 3 ? b011 3. if wc_cfg1[2:0]= 3 ? b001: wc_cfg0[14:12]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg1[2:0]= 3 ? b010: wc_cfg0[14:12] = 3 ? b011 4. if wc_cfg1[5:3]= 3 ? b001: wc_cfg0[17:15]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg1[5:3]= 3 ? b010:wc_cfg0[17:15] = 3 ? b011 6x6 matrix mode (matrix [4:3]= 2 ? b11) ? poll_en=1 ? in_en[9:4]= 6 ? b111111; in_en[15:10]= 6 ? b111111 ? mode[9:4] = 6 ? b000000; mode[15:10] = 6 ? b000000 ? cs_select[9:4]= 6 ? b111111; cs_select[15:10]= 6 ? b000000 ? iwett(csi) > iwett (cso): 1. wc_cfg0[20:18] > wc_cfg0[8:6] 2. wc_cfg0[23:21] > wc_cfg0[11:9] 3. wc_cfg1[2:0] > wc_cfg0[14:12] 4. wc_cfg1[5:3] > wc_cfg0[17:15] ? if tw event is expected, cso can only be set to 1ma or 2ma: 1. if wc_cfg0[8:6]= 3 ? b001: wc_cfg0[20:18]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg0[8:6]= 3 ? b010: wc_cfg0[20:18] = 3 ? b011 2. if wc_cfg0[11:9]= 3 ? b001: wc_cfg0[23:21]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg0[11:9]= 3 ? b010: wc_cfg0[23:21] = 3 ? b011 3. if wc_cfg1[2:0]= 3 ? b001: wc_cfg0[14:12]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg1[2:0]= 3 ? b010: wc_cfg0[14:12] = 3 ? b011 4. if wc_cfg1[5:3]= 3 ? b001: wc_cfg0[17:15]= 3 ? b010, 3 ? b011, 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111; if wc_cfg1[5:3]= 3 ? b010: wc_cfg0[17:15] = 3 ? b011 clean current polling (if ccp_inx= 1 in the ccp_cfg1 register) at least one input (standard or matrix) or the vs measurement has to be enabled: in_en_x= 1 in the in_en register or config [16]= 1 ? b1 (1) wetting current auto-scaling (if wc_cfg1 [22:21] != 2b ? 11) ? the wetting current auto-scaling feature is only activated in the continuous mode: poll_en= 0 (2) ? the wetting current auto-scaling only applies to 10ma or 15ma wetting currents: wc_inx bits = 3 ? b100, 3 ? b101, 3 ? b110, or 3 ? b111 in the wc_cfg0 and wc_cfg1 registers. (2) wetting current diagnostic (if config [21:18] != 4b ? 0000) ? at least one channel has to be enabled from in0 to in3 (in_en[3:0] != 4b ? 0000) ? inputs in0 to in3 need to be configured to adc input mode: mode[3:0] = 4 ? b1111 ? inputs in0 and in1 need to be configured to cso: cs select [1:0]= 2b ? 00 ? inputs in2 and in3 need to be configured to csi: cs select [3:2]= 2b ? 11 ? continuous mode ? standard polling mode t poll_time and t poll_act_time settings have to meet the below requirement: t poll_time 1.3 [ t poll_act_time + n 24 s + 10 s] (3) (4) ? n: the number of enabled channels configured in register in_en ? t poll_time : timing setting configured in config[4:1] ? t poll_act_time : timing setting configured in config[8:5]
114 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated programming guidelines (continued) table 59. TIC12400-Q1 programming guidelines (continued) category programming requirement matrix polling mode t poll_time ,t poll_act_time , and t poll_act_time_m settings have to meet the below requirement: t poll_time > 1.3 [ m t poll_act_time_m + t poll_act_time + n 24 s + 10 s] (3) (4) ? n: the number of enabled channels configured in register in_en ? m: 16 for 4x4 matrix; 25 for 5x5 matrix; 36 for 6x6 matrix ? t poll_time : timing setting configured in config[4:1] ? t poll_act_time_m : timing setting configured in matrix[2:0] ? t poll_act_time : timing setting configured in config[8:5]
115 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the TIC12400-Q1 is an advanced 24-input multiple switch detection interface (msdi) device designed to detect external mechanical switch status in a 12-v automotive system by acting as an interface between the switches and the low- voltage microcontroller. the device offers a number of unique features to replace systems implemented with discrete components, saving board space and reducing the bill of materials (bom). the device can also be configured into low-power polling mode, which provides significant savings on system power consumption. 9.2 using TIC12400-Q1 in a 12 v automotive system figure 85. typical system diagram of battery connections for TIC12400-Q1 the TIC12400-Q1 is designed to operate with a 12 v automotive system. figure 85 depicts a typical system diagram to show how the device is connected to the battery. care must be taken when connecting the battery directly to the device on the v s supply pin (through a reverse-blocking diode) or the input (in x ) pins since an automotive battery can be subjected to various transient and over-voltage events. manufacturers have independently created standards and test procedures in an effort to prevent sensitive electronics from failing due to these events. recently, combined efforts are made with iso to develop the iso 16750-2 standard (road vehicles -- environmental conditions and testing for electrical and electronic equipment -- part 2: electrical loads), which describe the possible transients that could occur to an automotive battery and specify test methods to simulate them. voltage regulator gnd vs vs inx vdd /int /cs sclk si so mosi miso sclk /cs /int vdd 12-v automotive battery TIC12400-Q1 mcu body control module sw agnd dgnd ep u s copyright ? 2016, texas instruments incorporated
116 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated using TIC12400-Q1 in a 12 v automotive system (continued) it shall be noted that the TIC12400-Q1 is designed and tested according to the iso 16750-2 standard. a few voltage stress tests and their test conditions are listed below. exposing the device to more severe transient events than described by the standard could potentially causes performance degradation and long-term damage to the device. ? direct current supply voltage: v bat, min = 6 v; v bat, max = 16 v ? to emulate a jump start event, voltage profile described in figure 86 is used. figure 86. voltage profile to test a jump start event table 60. voltage profile parameters to test a jump start event parameter value v bat, min 10.8 v v bat, max 24 v t r < 10 ms t 1 60 s 6 s t f < 10 ms number of cycles 1 ? to emulate a load dump event for an alternator with centralized load dump suppression, voltage profile described below is used. u a and u s * are applied directly to v bat . figure 87. voltage profile to test a load dump event with centralized load dump suppression t r t 1 t f v bat, max v bat, min v bat t
117 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 61. voltage profile used to test a load dump event with centralized load dump suppression parameter value u a 13.5 v u s 79 v us 101 u s * 35 v t d 40 ms t d 400 ms t r < 10 ms number of cycles 5 pulses at intervals of 1 min ? to emulate a cranking event, voltage profile describe below is used. u s , u s6 , and u a are applied directly to v bat . figure 88. voltage profile to test a cranking event table 62. voltage profile used to test a cranking event parameter value - level i value - level ii value - level iv u s6 8 v 4.5 v 6 v u s 9.5 v 6.5 v 6.5 v u a 14 v 0.2 v 14 v 0.2 v 14 v 0.2 v t f 5 ms 0.5 ms 5 ms 0.5 ms 5 ms 0.5 ms t 6 15 ms 1.5 ms 15 ms 1.5 ms 15 ms 1.5 ms t 7 50 ms 5 ms 50 ms 5 ms 50 ms 5 ms t 8 1000 ms 100 ms 10000 ms 1000 ms 10000 ms 1000 ms t r 40 ms 4 ms 100 ms 10 ms 100 ms 10 ms 9.3 resistor-coded switches detection in automotive body control module the body control module (bcm) is an electronic control unit responsible for monitoring and controlling various electronic accessories in a vehicle's body. detection of various mechanical switches status in a vehicle is one important task handled by the bcm. besides the typical on-and-off (or digital) type of switch, more sophisticated type of switches, called resistor-coded switches, can also be present in an automotive body control system. resistor-coded switches have more than 2 unique switch states, and are often used for implementation of wiper, illumination, and signal control arms in a vehicle. due to various voltage potentials generated by different positions of a resistor-coded switch, an adc, typically inside the microcontroller, is used to detect the different states of the switch. the TIC12400-Q1 can natively support monitoring of an resistor-coded switch with its integrated 10-bit adc and configurable thresholds. the following application diagram depicts how the tic12400- q1 is used in a bcm to detect external mechanical resistor-coded switches and a detailed design example is shown in the following sections.
118 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated resistor-coded switches detection in automotive body control module (continued) figure 89. using TIC12400-Q1 to monitor a resistor-coded switch in body control module application 9.3.1 design requirements figure 90. example 3-state resistor-coded switch table 63. example resistor-coded switch specification specification min max v bat 9 v v bat 16 v 9 v 16 v r 1 680 8% 625.6 734.4 r sw1 50 max when closed 0 50 sw sw + v gnd_shift gnd r sw_equ r 1 r sw2 r sw1 r dirt voltage regulator gnd vs vs inx sw vdd /int /cs sclk si so mosi miso sclk /cs /int vdd vbat TIC12400-Q1 mcu body control module sw resistor- coded switch copyright ? 2016, texas instruments incorporated
119 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated resistor-coded switches detection in automotive body control module (continued) table 63. example resistor-coded switch specification (continued) specification min max r sw2 50 max when closed 0 50 r dirt 5000 min 5000 v gnd_shift 1 v -1 +1 an example of a 3-state resistor-coded switch is shown in figure 90 , with table 63 summarizing its detailed specification. the goal of this design is to utilize the TIC12400-Q1 ? s integrated adc to detect and differentiate the 3 switch states: 1. state 1: both sw1 and sw2 open 2. state 2: sw1 open and sw2 closed 3. state 3: sw1 closed and sw2 open to mimic real automotive systems, the battery is assumed to be fluctuating between 9 v and 16 v. r dirt is introduced to model the small leakage flowing across the switch in open state. there is also a 1 v ground shift present in the system, meaning there could be up to 1 v of potential difference between the switch reference point and the ground reference of the TIC12400-Q1. when the switch changes position and the switch state changes from one to another, the TIC12400-Q1 is required to correctly detect the state transition and issue an interrupt to alert the microcontroller. the switch information needs to be stored in the status registers for the microcontroller to retrieve. 9.3.2 detailed design procedure table 64. detailed design procedure step 1 step 2 step 3 step 4 step 5 equivalent resistance value ( ) v inx (v) v inx + v gnd_shift (v) adc code spread threshold min max min max min max min max state 1: both sw1 and sw2 open 5000 > 6 v - > 6 v - 1023 - state 2: sw1 open and sw2 closed 555.95 678.03 2.391 3.797 1.391 4.797 237 818 921 state 3: sw1 closed and sw2 open 0 49.5 0 0.277 0 1.277 0 218 228 use the following procedures to calculate thresholds to program to the TIC12400-Q1 for proper switch detection: 1. calculate the equivalent resistance values at different switch states, taking into account r dirt and the 8% resistance variation. 2. estimate the voltage established when wetting current flows through the switch by utilizing the relationship v inx = r sw_equ i wett_act , where r sw_equ is the equivalent switch resistance value and i wett_act is the actual wetting current flowing through the switch. the 5 ma wetting current setting is selected in this design, because it best uses the dynamic range of the adc (from 0 to 6 v). the wetting current, however, can vary depending on manufacturing process variation and operating temperature, and needs to be taken into account. referring to the electrical table of the TIC12400-Q1 and assuming enough headroom for the current source (cso) to operate, the 5ma wetting current setting produces current ranging between 4.3 ma and 5.6 ma. the voltage established on the TIC12400-Q1 input pin (v inx ) can be calculated accordingly. 3. take the ground shift non-ideality into account. as defined in design requirements , the ground shift can be varying between 1 v. therefore, effectively, the actual voltage seen at the TIC12400-Q1 can also vary up to 1 v. 4. convert the voltage established on the inx pin into equivalent adc code. the full-scale range of the 10-bit adc is from 0 v to 6 v, with 6 v corresponding to the max code of 1023. therefore, the adc code spread for each of the 3 different switch states can be calculated accordingly. 5. after the adc code spread for each switch state is calculated, the detection threshold can be chosen to be the mid-point between the upper and lower codes of two neighboring states to give best margin for detection.
120 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.3.3 application curves figure 91. measured adc code distribution for the 3 switch states switch status adc code 0 1 2 3 0 150 300 450 600 750 900 1050 1200 1350 1500 d001d001 sw1 closed (max code = 216) sw2 closed (min code = 301) (max code = 770) both sw1 and sw2 open (code = 1023)
121 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 10 power supply recommendations there are two supply input pins for the TIC12400-Q1: v s and v dd . v s is the main power supply for the entire chip and is essential for all critical functions of the device. the v s supply is designed to be connected to a 12-v automotive battery (through a reverse blocking diode) with nominal operating voltage no greater than 16v. the v dd supply is used to determine the logic level on the spi communication interface, source the current for the so driver, and sets the pull-up voltage for the /cs pin. it can also be used as a possible external pull-up supply for the /int pin as an alternative to the v s supply and it shall be connected to a 3 v to 5.5 v logic supply. removing v dd from the device disables spi communications, but does not impact normal operation of the device. to improve stability of the supply inputs, some decoupling capacitors are recommended on the pcb. figure 92 shows an example on the on-board power supply decoupling scheme. the battery voltage (v bat ) is decoupled on the electronic control unit (ecu) board using a large decoupling capacitor (c buff ). the diode is installed to prevent damage to the internal system under reversed battery condition. c vs shall be installed close to the TIC12400-Q1 for best decoupling performance. the voltage regulator provides a regulated voltage for the digital portion of the device and for the local microcontroller and its output is decoupled with c decouple . table 65 lists recommended values for each individual decoupling capacitor shown in the system diagram. table 65. decoupling capacitor recommendations crc rule value c buff 100 f, 50 v rated, 20% c vbat 100 nf, 50v rated, 10%; x7r c vs 100 nf, 50 v rated c decouple 100 nf~1 f figure 92. recommended power supply decoupling TIC12400-Q1 voltage regulator gnd 37 38 vs vs mcu 19 vdd vdd v bat copyright ? 2016, texas instruments incorporated ecu connector c vbat c buff c vs c decouple electronic control unit (ecu)
122 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 layout 11.1 layout guidelines figure 93 illustrates an example of a pcb layout with the TIC12400-Q1. some key considerations are: 1. decouple the v s and v dd pins with capacitor using recommended values from section power supply recommendations and place them as close to the pin as possible. make sure that the capacitor voltage rating is sufficient for the v s and v dd supplies. 2. keep the input lines as short as possible. 3. use a solid ground plane to help distribute heat and reduce electromagnetic interference (emi) noise pickup. 4. do not run sensitive analog traces in parallel with digital traces. avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary. 5. to achieve good thermal performance, the exposed thermal pad underneath the device must be soldered to the board and flooded with vias to ground planes. for simple double-sided pcbs where there are no internal layers, the surface layers can be used to remove heat. for multilayer pcbs, internal ground planes can be used for heat removal. 7. minimize the inductive parasitic between the inx input capacitors and the thermal pad ground return.
123 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11.2 layout example figure 93. example layout in13 in14 in15 in16 in17 in18 in19 in20 agnd in21 in22 in23 in0 in1 sclk siso vdd vsvs in12 in11 in10 in9 in8 in7 in6 in5 dgnd in4 in3 in2 /int cap_d cap_pre reset cap_a not to scale /cs via to ground plane via to ground plane via to ground plane via to ground plane vias to ground plane and heat sink of the pcb via to ground plane via to ground plane c r r cc c c c
124 TIC12400-Q1 scps260 ? august 2017 www.ti.com product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
125 TIC12400-Q1 www.ti.com scps260 ? august 2017 product folder links: TIC12400-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 21-aug-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tic12400qdcprq1 preview htssop dcp 38 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 tic12400q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
important notice texas instruments incorporated (ti) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ti ? s published terms of sale for semiconductor products ( http://www.ti.com/sc/docs/stdterms.htm ) apply to the sale of packaged integrated circuit products that ti has qualified and released to market. additional terms may apply to the use or sale of other types of ti products and services. reproduction of significant portions of ti information in ti data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such reproduced documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyers and others who are developing systems that incorporate ti products (collectively, ? designers ? ) understand and agree that designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that designers have full and exclusive responsibility to assure the safety of designers ' applications and compliance of their applications (and of all ti products used in or for designers ? applications) with all applicable regulations, laws and other applicable requirements. designer represents that, with respect to their applications, designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. designer agrees that prior to using or distributing any applications that include ti products, designer will thoroughly test such applications and the functionality of such ti products as used in such applications. ti ? s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? ti resources ? ) are intended to assist designers who are developing applications that incorporate ti products; by downloading, accessing or using ti resources in any way, designer (individually or, if designer is acting on behalf of a company, designer ? s company) agrees to use any particular ti resource solely for this purpose and subject to the terms of this notice. ti ? s provision of ti resources does not expand or otherwise alter ti ? s applicable published warranties or warranty disclaimers for ti products, and no additional obligations or liabilities arise from ti providing such ti resources. ti reserves the right to make corrections, enhancements, improvements and other changes to its ti resources. ti has not conducted any testing other than that specifically described in the published documentation for a particular ti resource. designer is authorized to use, copy and modify any individual ti resource only in connection with the development of applications that include the ti product(s) identified in such ti resource. no other license, express or implied, by estoppel or otherwise to any other ti intellectual property right, and no license to any technology or intellectual property right of ti or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti products or services are used. information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. use of ti resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. ti resources are provided ? as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

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